LAN8804SLASHZMXC1 datasheet(56/91 Pages) MICROCHIP

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LAN8804

DS00003591G-page 56

To further reduce power usage, the crystal oscillator maybe disabled by setting the enXTALb bit in the Analog Control

Since the MII Management Interface operates using the crystal clock, once this bit is set, the device will become inac-

cessible. A pin reset or power cycle is required to resume operation.

5.20 PLL/Clocks and Resets

The device provides the following PLLs:

•

System PLL: Generates the internal system clocks and clocks required for the internal PHYs. See Section 5.20.1,

"System Clocks" for additional information.

•

QSGMII SerDes MPLL: Generates the clocks needed by the SerDes. See Section 5.20.2, "QSGMII SerDes

Clock" for additional information.

The reference clock selection of the System PLL and QSGMII SerDes MPLL are controlled via the

REF_CLK_SEL[1:0]

pins. Refer to Table 3-5 for detailed

REF_CLK_SEL[1:0] setting information.

5.20.1

SYSTEM CLOCKS

System clocks are generated by the System PLL and are used for many common (not port-specific) functions such as

QSGMII TX and configuration registers. These clocks are also selectable by each PHY port for use as PHY TX timing.

The System PLL generates the following clocks:

• 250 MHz system clock

• 25 MHz system clock

The System PLL can use any of the following as its input reference clock:

• 25 MHz Crystal

• 25 MHz system single-ended reference clock input

• 125 MHz system differential clock inputs

5.20.2

QSGMII SERDES CLOCK

The 250 MHz QSGMII SerDes clock is generated by the SerDes MPLL.

The QSGMII SerDes MPLL can use any of these as its input reference clock:

• 25 MHz system clock (from crystal or single-ended external clock input)

• 125 MHz system differential clock inputs

5.20.3

RESETS

The device supports the following software resets from configuration registers:

• Chip hard and soft resets (all logic and macros in the chip)

- Chip soft reset (EP4.9) does not reset the Gigabit PHYs. If needed, the GPHY Hard Macro soft reset must be

used for this.

- GPHY resistor calibration is also run based on the chip hard reset.

• QSGMII hard and soft resets (QSGMII SerDes, extender, and per-port PCS1Gs)

• QSGMII SerDes transmitter and receiver resets

• Port hard and soft resets (all port-specific logic and macros in each port)

- Neither port hard reset (EP5.80) nor soft reset (EP5.81) will reset the GPHY. If needed, the GPHY Macro hard

or soft reset must be used for this.

• Gigabit PHY hard macro hard and soft resets (per port)

Note:

Coma mode has no effect on these functions. Refer to Section 5.18, "Coma Mode" for additional informa-

tion.

LAN8804/ZMXC1 Datasheet(PDF) 56 Page - Microchip Technology

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