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PC87332VLJ Datasheet(PDF) 96 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de pieza PC87332VLJ
Descripción Electrónicos  PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
PDF  98 Pages
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Fabricante Electrónico  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87332VLJ Datasheet(HTML) 96 Page - National Semiconductor (TI)

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90 Electrical Characteristics (Continued)
9315 Enhanced Parallel Port Timing
Symbol
Parameter
Conditions
Min
Max
Units
tWW
WRITE Active from WR Active (Note 1)
45
ns
tWST
DSTRB or ASTRB Active from
EPP 17
45
ns
WR Active (Notes 1 2)
EPP 19
65
ns
tWEST
DSTRB or ASTRB Active after
EPP 17
0
ns
WRITE Active
EPP 19
10
ns
tWPDh
PD0 – 7 Hold after DSTRB or ASTRB Inactive
50
ns
tHRW
IOCHRDY Active after WAIT Active
EPP 17
40
ns
(Note 3)
tWPDS
PD0 – 7 Valid after WRITE Active
D0 – 7 is Stable 15 ns
15
ns
before WR Active
tEPDW
PD0 – 7 Valid
80
ns
tEPDh
PD0 – 7 Invalid after DSTRB or ASTRB Inactive
0
ns
tZWSa
ZWS Valid after WR or RD Active
45
ns
tZWSh
ZWS Hold after WR or RD Inactive
0
ns
Note 1
tWST and tWW are valid in EPP 19 only if WAIT is low when WR becomes active else tWST and tWW are measured from WAIT
Note 2
The PC87334 design guarantees that WRITE will not change from low to high before DSTRB or ASTRB goes from low to high
Note 3
In EPP 19 IOCHRDY is measured from WR or RD
TLC11930 – 42
FIGURE 9-17 Enhanced Parallel Port Timing
96



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