PC87332VLJ datasheet(76/98 Pages) NSC

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70 Parallel Port (Continued)

76 EXTENDED CAPABILITIES PARALLEL PORT (ECP)

761 Introduction

The ECP support includes a 16-byte FIFO that can be con-

figured for either direction commanddata FIFO tags (one

per byte) a FIFO threshold interrupt for both directions

FIFO empty and full status bits automatic generation of

strobes (by hardware) to fill or empty the FIFO transfer of

commands and data and a Run Length Encoding (RLE) ex-

panding (decompression) as explained below

The Extended Capabilities Port (ECP) is enabled when bit 2

of PCR is 1 Once enabled its mode is controlled via the

mode field of ECRbits 5 6 7 of the ECR register

The ECP has ten registers See Table 7-7

The AFIFO CFIFO DFIFO and TFIFO registers access the

same ECP FIFO The FIFO is accessed at Base a 000h or

Base a 400h depending on the mode field of ECR and the

The FIFO can be accessed by host DMA cycles as well as

host PlO cycles

When DMA is configured and enabled (bit 3 of ECR is 1 and

bit 2 of ECR is 0) the ECP automatically (by hardware) is-

sues DMA requests to fill the FIFO (in the forward direction

when bit 5 of DCR is 0) or to empty the FIFO (in the back

ward direction when bit 5 of DCR is 1) All DMA transfers are

to or from these registers The ECP does not assert a DMA

request for more than 32 consecutive DMA cycles The ECP

stops requesting DMA when Terminal Count TC is detect-

ed during an ECP DMA cycle

A write operation to a full FIFO or a read operation from an

empty FIFO are ignored The written data is lost and the

read data is undefined The FIFO empty and full status bits

are not affected by such an access

Some registers are not accessible in all modes of operation

or may be accessed in one direction only Accessing a non-

accessible register has no effect Data read is undefined

data written is ignored the FIFO does not update The

PC87334 Parallel Port registers (DTR STR and CTR) are

not accessible when ECP is enabled

To improve noise immunity in ECP cycles the state ma-

chine does not examine the control handshake response

lines until the data has had time to switch

In ECP mode

DATAR replaces DTR of SPPEPP

DSR replaces SPR of SPPEPP

DCR replaces CTR of SPPEPP

A detailed description of the various modes follow in Sec-

tions 78 – 711

TABLE 7-7 ECP Registers Summary

A10

Offset

Access

Size

Mode

Function

Address

ECR (5 – 7)

DATAR

Byte

000001

Parallel Port Data Register

AFIFO

Byte

011

ECP Address FIFO

DSR

Byte

ALL

Status Register

DCR

Byte

ALL

Control Register

CFIFO

Byte

010

Parallel Port Data FIFO

DFIFO

Byte

011

ECP Data FIFO

TFIFO

Byte

110

Test FIFO

CNFGA

Byte

111

Configuration Register A

CNFGB

Byte

111

Configuration Register B

ECR

Byte

ALL

Extended Control Register

Note

The Base address is stored in bits A2–A9 It is 278h 378h or 3BCh as specified in the FAR register

PC87332VLJ Datasheet(PDF) 76 Page - National Semiconductor (TI)

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