PC87332VLJ datasheet(68/98 Pages) NSC

68 / 98 page

60 Serial Ports (Continued)

Bits 6 7

The combination of FCR6 and FCR7 is used to

designate the interrupt trigger level (see

Figure

62 ) When the number of bytes in the RCVR FIFO

equals the designated interrupt trigger level a Re-

ceived Data Available Interrupt is activated This

interrupt must be enabled by setting the Interrupt

Enable Register (IER) bit 0

FCR Bits

Trigger Level (Bytes)

RCVR FIFO

FIGURE 6-2 Receiver FIFO Trigger Level

66 INTERRUPT IDENTIFICATION REGISTER (IIR)

In order to provide minimum software overhead during data

character transfers the UART prioritizes interrupts into four

levels and records these in the Interrupt Identification Reg-

ister The four levels of interrupt conditions in order of priori-

ty are Receiver Line Status Received Data Ready Trans-

mitter Holding Register Empty and MODEM Status

When the CPU accesses the IIR the UART freezes all inter-

rupts and indicates to the CPU which pending interrupt has

the highest priority While the CPU accesses this interrupt

routine the UART records new interrupts but does not

change its current indication until the current access is com-

plete Table 6-2 shows the contents of the IIR Details on

each bit follow

Bit 0

This bit can be used in an interrupt environment to

indicate whether an interrupt condition is pending

When it is 0 an interrupt is pending and the IIR

contents may be used as a pointer to the appropri-

ate interrupt service routine When it is 1 no inter-

rupt is pending See Table 6-5

Bits 1 2

These two bits of the IIR are used to identify the

highest priority interrupt pending as indicated in

Table 6-5

Bit 3

In the 16450 mode this bit is 0 In the FIFO mode it

is set along with bit 2 when a time-out interrupt is

pending See Table 6-5

Bits 4 5

These bits of the IIR are always 0

Bits 6 7

These two bits are set when FCR0 e 1 (FIFO

Mode enabled)

TABLE 6-5 PC87332 Interrupt Control Functions

Interrupt Identification

Interrupt Set and Reset Functions

Bit 3

Priority

Level

(FIFO Mode

Bit 2

Bit 1

Bit 0

Interrupt Type

Interrupt Source

Interrupt Reset Control

Only)

None

Highest Receiver Line Status

Overrun Error Parity Error

Reading the Line

Framing Error or Break

Status Register

Interrupt

Second Received Data Available Receiver Data Available

Read Receiver Buffer

Second Character

No Characters have been

Reading the Receiver

(FIFO

Time-Out

removed from or input to the

Buffer Register

mode

Indication

RCVR FIFO during the last 4

only)

char times and there is at least

1 char in it during this time

Third

Transmitter Holding

Reading the IIR Register

(if Source of Interrupt) or

Writing the Transmitter

Holding Register

Fourth MODEM Status

Clear to Send or Data Set

Reading the MODEM

Ready or Ring Indicator

Status Register

or Data Carrier Detect

PC87332VLJ Datasheet(PDF) 68 Page - National Semiconductor (TI)

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