PC87332VLJ datasheet(74/98 Pages) NSC

74 / 98 page

70 Parallel Port (Continued)

6 Only if no EPP write is pending when WAIT goes low (or

when bit 7 of PTR is 1 and the direction is changed to

Backwards by setting bit 5 of CTR to 1) the EPP pulls

WRITE to high

If an EPP write is pending WRITE remains low and the

EPP may change PD0 – 7

TLC11930 – 18

FIGURE 7-4 EPP 19 Address Write

EPP 19 Address Read

The following procedure reads from the address register

See also

Figure 7-5

1 The host reads a byte from the EPP address register

When RD goes low the EPP pulls IOCHRDY low and

waits for WAIT to go low

2 When WAIT goes low the EPP pulls ASTRB low and

waits for WAIT to go high

If wait was already low steps 2 and 3 occur concurrently

3 When WAIT goes high the EPP stops pulling IOCHRDY

low latches PD0 – 7 and pulls ASTRB high

4 When RD goes high the EPP pins D0 – 7 are at TRI-

STATE

EPP 19 Data Write and Data Read

This procedure writes to the selected peripheral drive or

Figure 7-5

EPP 19 data read and write operations are similar to EPP

19 address read and write operations respectively except

that the data strobe (DSTRB signal) and a data register re-

place the address strobe (ASTRB signal) and the address

TLC11930 – 19

FIGURE 7-5 EPP 19 Address Read

Parallel Port Multiplexor (PPM)

A PPM is used for a PC to interface with either a printer or

an external FDD via a 25-pin DIN connector It may have an

internal Floppy Disk Drive (FDD) connected via regular FDC

pins The printer and external FDD may be switched without

turning the PC off and without updating the DOS device

tables The software may assign ‘‘A’’ to the FDD connected

to the regular FDC pins and ‘‘B’’ to the FDD connected to

the PPM pins (the default assignment) or vice versa

The Multiplexors

1 The FDC output signals are always connected to the reg-

ular FDC output pins

The FDC output signals are connected to the PPM output

pins when the PPM is enabled (bit 2 of FCR is 1) and a

floppy drive is connected to it (PFN e 0)

(See

Table 7-5)

The FDC input signals are connected to the regular FDC

pins when either bit 2 of FCR is 0 or PNF e 1

The FDC input pins are internally multiplexed between

the regular FDC pins and the PPM pins when bit 2 of FCR

is 1 and PNF e 0 as follows

the PPM pins are connected to the FDC input signals

when DR1 e 0

the regular pins are connected to the FDC input sig-

nals when DR1 e 1

2 Floating the PPM pins

To support ‘‘true’’ floating pins the pins are back-drive

protected

When bit 3 of FCR is 1 the PPM pins are floated

PC87332VLJ Datasheet(PDF) 74 Page - National Semiconductor (TI)

PC87332VLJ Datasheet(HTML) 74 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

Datasheet Descarga

Enlace URL