PC87332VLJ datasheet(31/98 Pages) NSC

31 / 98 page

30 FDC Register Description (Continued)

D4 – 2

Precompensation Select

These three bits select

the amount of write precompensation the floppy

controller uses on the WDATA disk interface output

Table 3-5 shows the amount of precompensation

used for each bit pattern In most cases the default

values (Table 3-6) can be used however alternate

values can be chosen for specific types of drives

and media Track 0 is the default starting track num-

ber for precompensation The starting track number

can be changed in the Configure command

TABLE 3-5 Write Precompensation Delays

Bits 4 3 2

Precompensation Delay

TUP Bit 0e1

TUP Bit 1e1

24 MHz

48 MHz

111

00 ns

001

417 ns

208 ns

010

833 ns

417 ns

011

1250 ns

625 ns

100

1667 ns

833 ns

101

2083 ns

1042 ns

110

2500 ns

1250 ns

000

DEFAULT

TABLE 3-6 Default Precompensation Delays

Data Rate

Precompensation Delay

(24 MHz and 48 MHz)

2 Mbps

208 ns

1 Mbps

417 ns

500 kbps

1250 ns

300 kbps

1250 ns

250 kbps

1250 ns

D1 – 0

Data Rate Select 10

These bits determine the

data rate for the floppy controller See Table 3-7 for

the corresponding data rate for each D10 value

pair The data rate select bits are unaffected by a

software reset and are set to 250 kbps after a hard-

ware reset

TABLE 3-7 Data Rate Select Encoding

Bit 1

TUP

Data Rate Select

MFM

1 Mbps

500 kbps

300 kbps

250 kbps

2 Mbps

Illegal

This feature is not tested

317 Data Register (FIFO)

ReadWrite

The FIFO (readwrite) is used to transfer all commands

data and status between the mP and the FDC During the

Command Phase the mP writes the command bytes into the

FIFO after polling the RQM and DIO bits in the MSR During

the Result Phase the mP reads the result bytes from the

FIFO after polling the RQM and DIO bits in the MSR

Enabling the FIFO and setting the FIFO threshold is done

via the Configure command If the FIFO is enabled only the

Execution Phase byte transfers use the 16-byte FIFO The

FIFO is always disabled during the Command and Result

Phases of a controller operation A software reset will not

disable enabled FIFO if the Lock bit is set in the Lock Com-

mand After a hardware reset the FIFO is disabled to main-

tain compatibility with PC-AT systems

The 16-byte FIFO can be used for DMA Interrupt or soft-

ware polling type transfers during the execution of a read

write format or scan command In addition the FIFO can

be put into a Burst or Non-Burst mode with the Mode com-

mand In the Burst mode DRQ or IRQ6 remains active until

all of the bytes have been transferred to or from the FIFO In

the Non-Burst mode DRQ or IRQ6 is deasserted for 350 ns

to allow higher priority transfer requests to be serviced

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