PC87332VLJ datasheet(47/98 Pages) NSC

47 / 98 page

40 FDC Command Set Description (Continued)

3 The Ready Signal changed state during the polling mode

for an internally selected drive (Occurs only after a hard-

ware or software reset)

4 A Seek Relative Seek or Recalibrate command termi-

nates

An interrupt due to reasons 1 or 2 does not require the

Sense Interrupt command and is cleared automatically This

type of interrupt occurs during normal command operations

and is easily discernible by the mP via the MSR It is cleared

when reading or writing information from or to the Data Reg-

ister (FIFO)

An interrupt caused by reasons 3 or 4 is identified with the

aid of the Sense Interrupt command This type of interrupt is

cleared after the first result byte has been read Use bits 5

6 and 7 of ST0 to identify the cause of the interrupt as

shown in Table 4-14

Issuing a Sense Interrupt command without an interrupt

pending is treated as an Invalid command If the extended

track range mode is enabled a third byte should be read in

the Result Phase which will indicate the four most signifi-

cant bits of the present track number Otherwise only two

result bytes should be read

TABLE 4-14 Status Register 0 Termination Codes

Status Register 0

Cause

Interrupt

Seek

Code

End

Internal Ready Went True

Normal Seek Termination

Abnormal Seek Termination

4119 Set Track Command

This command is used to inspect or change the value of the

internal Present Track Register This can be useful for re-

covery from disk mistracking errors where the real current

track can be read through the Read ID command and then

the Set Track command can be used to set the internal

Present Track Register to the correct value

If the WNR bit is a 0 a track register is to be read In this

case the Result Phase byte contains the value in the inter-

nal register specified and the third byte in the Command

Phase is a dummy byte

If the WNR bit is a 1 data is written to a track register In this

case the third byte of the Command Phase is written to the

specified internal track register and the Result Phase byte

contains this new value

The DS1 and DS0 bits select the Present Track Register for

the particular drive The internal register address depends

on MSB DS1 and DS0 as shown in Table 4-15 This com-

mand does not generate an interrupt

TABLE 4-15 Set Track Register Address

DS1

DS0

MSB

PTR0 (LSB)

PTR0 (MSB)

PTR1 (LSB)

PTR1 (MSB)

PTR2 (LSB)

PTR2 (MSB)

PTR3 (LSB)

PTR3 (MSB)

Command Phase

WNR

MSB

DS1

DS0

Present Track Number (PTR)

Execution Phase

Internal register selected by MSB of DS1

or DS0 is read or written

Result Phase

Value

4120 Specify Command

The Specify command sets the initial values for three inter-

nal timers The parameters of this command are undefined

after power-up and are unaffected by any reset Thus soft-

ware should always issue a Specify command as part of an

initialization routine This command does not generate an

interrupt

Command Phase

0000001

Step Rate Time

Motor Off Time

Motor On Time

DMA

Execution Phase

Internal registers are written

Result Phase

None

Step Rate Time

These four bits define the time interval

between successive step pulses during a seek implied

seek recalibrate or relative seek The programming of this

step rate is shown in Table 4-16

TABLE 4-16 Step Rate Time (SRT) Values

Data Rate

Value

Range

Units

1 Mbps

(16 b SRT)2

05 – 8

500 kbps

(16 b SRT)

1 – 16

300 kbps

(16 b SRT) c 167

167 – 267

250 kbps

(16 b SRT) c 2

2–32

Motor Off Time

These four bits determine the simulated

Motor Off time as shown in Table 4-17

Motor On Time

These seven bits determine the simulated

Motor On time as shown in Table 4-18

DMA

This bit selects the data transfer mode in the Execu-

tion Phase of a read write or scan operation

0 e

DMA mode is selected

1 e

Non-DMA mode is selected

PC87332VLJ Datasheet(PDF) 47 Page - National Semiconductor (TI)

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