PC87332VLJ datasheet(70/98 Pages) NSC

70 / 98 page

70 Parallel Port

71 INTRODUCTION

This parallel interface is designed to provide all of the sig-

nals and registers needed to communicate through a stan-

dard parallel printer port as found in the IBM PC-XT PC-AT

PS2 and Centronics systems This parallel port supports

three standard modes of operation SPP EPP ECP The

Standard Parallel Port (SPP) is a software based protocol

with performance of up to 150 kbps

The Enhanced Parallel Port (EPP) is a hardware protocol

which offers up to 2 Mbps

The Extended Capabilities Port (ECP) is also a hardware

protocol with up to 2 Mbps transfer rate In addition the

ECP has FIFO’s for receive and transmit and DMA support

to reduce the CPU overhead The ECP mode 0 is in fact

compatible with the SPP mode The ECP specification de-

fines the ACDC parameters of the signals to allow fast

communication without termination problems

All the above standards are incorporated into the 1284 IEEE

specifications

The address decoding of the registers utilizing A0 and A1 is

shown in Table 7-1 Table 7-3 shows the Reset states of

Parallel port registers and pin signals These registers are

shown in Section 72 to Section 74

TABLE 7-1 Parallel Interface Register Addresses

Address

Access

Data

ReadWrite

Status

Read

Control

ReadWrite

TRI-STATE

Special circuitry provides protection against damage that

might be caused when the printer is powered but the

PC87332 is not

There are two Standard Parallel Port (SPP) modes of opera-

tion (Compatible and Extended see Table 7-2) two En-

hanced Parallel Port (EPP) modes of operation and one Ex-

tended Capabilities Port (ECP) mode to complete a full IEEE

1284 parallel port

TABLE 7-2 Standard Parallel Port Modes Selection

Port Function

PTR7

Compatible

Extended

In Compatible mode a write operation causes the data to be

presented on pins PD0 – 7 A read operation in this mode

causes the Data Register to present the last data written to

it by the CPU See Table 7-3

In the Extended mode a write operation to the data register

causes the data to be latched If the Data Port Direction bit

(Control Register (CTR) bit 5) is 0 the latched data is pre-

sented to the pins and a read operation from this register

allows the CPU to read the last data it wrote to the port If

CTR5 is 1 the data is only latched and a read from this

See Table 7-2

TABLE 7-3 SPP Data Register Read and Write Modes

PTR7

CTR5

Result

Data Written to PD0 – 7

Data Read from the Output

Latch

Data Written to PD0 – 7

Data Written is Latched

Data Read from the Output

Latch

Data Read from PD0 – 7

72 DATA REGISTER (DTR)

TLC11930 – 12

This is a bidirectional data port that transfers 8-bit data The

direction is determined by the Power and Test Configuration

the CTR5 bit will determine the data direction in conjunction

with the Read and Write strobes When PTR7 bit is low the

parallel port operates in the output mode only The reset

value of this register is 0 See Table 7-3

73 STATUS REGISTER (STR)

TLC11930 – 13

This register provides status for the TIMEOUT ERROR

SLCT PE ACK and BUSY signals for a connected printer

It is a read only register Writing to it is an invalid operation

that has no effect

Bit 0

When in EPP mode this is the timeout status bit

When this bit is 0 no timeout

When this bit is 1 timeout occurred on EPP cycle

(minimum 10 msec) It is cleared to 0 after STR is

read ie consecutive reads (after the first read) al-

ways return 0 It is also cleared to 0 when EPP is

enabled (bit 0 of PCR is changed from 0 to 1)

When not in EPP mode this bit is 1

Bit 1

Reserved this bit is always 1

Bit 2

In the compatible mode (PTR7 bit is 0) or in ECP and

EPP mode with bit 4 of PCR e 0 this bit is always

one

In the Extended Mode (PTR7 bit is 1) or in ECP and

EPP with bit 4 of PCR e 1 this bit is the IRQ Status

bit

PC87332VLJ Datasheet(PDF) 70 Page - National Semiconductor (TI)

PC87332VLJ Datasheet(HTML) 70 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

Datasheet Descarga

Enlace URL