PC87332VLJ datasheet(30/98 Pages) NSC

30 / 98 page

30 FDC Register Description (Continued)

D4 – 2

Reserved

These bits are ignored

D1 0

Tape Select 10

These bits assign a logical drive

number to a tape drive Drive 0 is not available as a

tape drive and is reserved as the floppy disk boot

drive See Table 3-4 for the tape drive assignment

values

TABLE 3-3 Media ID Bit Functions

Bit 7

Bit 6

Bit 5

Media Type

Invalid Data

525

288M

144M

720k

TABLE 3-4 Tape Drive Assignment Values

TAPESEL1

TAPESEL0

Drive

Selected

None

315 Main Status Register (MSR)

Read Only

The read-only Main Status Register (MSR) indicates the cur-

rent status of the disk controller The MSR is always avail-

able to be read One of its functions is to control the flow of

data to and from the Data Register (FIFO) The MSR indi-

cates when the disk controller is ready to send or receive

data through the Data Register It should be read before

each byte is transferred to or from the Data Register except

during a DMA transfer No delay is required when reading

this register after a data transfer

After a hardware or software reset or recovery from a pow-

er-down state the MSR is immediately available to be read

by the mP It contains a value of 00h until the oscillator

circuit has stabilized and the internal registers have been

initialized When the FDC is ready to receive a new com-

mand it reports an 80h to the mP The system software can

poll the MSR until it is ready The worst case time allowed

for the MSR to report an 80h value (RQM set) is 25 ms after

reset or power-up

MSR

DESC

RQM

DIO

NON

CMD

DRV3

DRV2

DRV1

DRV0

DMA

PROG

BUSY

RESET

0000

COND

Request for Master

Indicates that the controller is

ready to send or receive data from the mP through

the FIFO This bit is cleared immediately after a byte

transfer and is set again as soon as the disk con-

troller is ready for the next byte During a Non-DMA

Execution phase the RQM indicates the status of

the interrupt pin

Data IO (Direction)

Indicates whether the con-

troller is expecting a byte to be written to (0) or read

from (1) the Data Register

Non-DMA Execution

Indicates that the controller

is in the Execution Phase of a byte transfer opera-

tion in the Non-DMA mode This mode can be used

for multiple byte transfers by the mP in the Execu-

tion Phase via interrupts or software polling

Command in Progress

This bit is set after the first

byte of the Command Phase is written This bit is

cleared after the last byte of the Result Phase is

read If there is no Result Phase in a command the

bit is cleared after the last byte of the Command

Phase is written

Drive 3 Busy

Set after the last byte of the Com-

mand Phase when a Seek or Recalibrate command

is issued for drive 3 Cleared after reading the first

byte in the Result Phase of the Sense Interrupt

Command for this drive

Drive 2 Busy

Same as D3 above but for drive 2

Drive 1 Busy

Same as D3 above but for drive 1

Drive 0 Busy

Same as D3 above but for drive 0

316 Data Rate Select Register (DSR)

Write Only

This write-only register is used to program the data rate

amount of write precompensation power-down mode and

software reset The data rate is programmed via the CCR

not the DSR for PC-AT Model 30 and MicroChannel appli-

cations Other applications can set the data rate in the DSR

The data rate of the floppy controller is determined by the

most recent write to either the DSR or CCR The DSR is

unaffected by a software reset A hardware reset sets the

DSR to 02h which corresponds to the default write precom-

pensation setting and a 250 kbps data rate

DSR

DESC

LOW

PRE-

DRATE1 DRATE0

RESET POWER

COMP2 COMP1 COMP0

RESET

COND

Software Reset

This bit has the same function as

the DOR RESET (D2 see Section 33) except that

this software reset is self-clearing

Low Power

Placinga1in this bit puts the control-

ler into the Manual Low Power mode The oscillator

and data separator circuits are turned off Manual

Low Power can also be accessed via the Mode

command The chip comes out of low power after a

software reset or access to the Data Register or

Main Status Register

Undefined Should be set to 0

PC87332VLJ Datasheet(PDF) 30 Page - National Semiconductor (TI)

PC87332VLJ Datasheet(HTML) 30 Page - National Semiconductor (TI)

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