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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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6MPS5 Datasheet(PDF) 97 Page - Texas Instruments |
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6MPS5 Datasheet(HTML) 97 Page - Texas Instruments |
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97 / 101 page  www.national.com 96 tX2l 36 X2 low time, external clock At 0.8V level (both edges) 0.5 Tclk - 500 tIs 42 Input setup time ISE Before R.E. CLK 12 tIh 42 Input hold time ISE, NMI, RXD1, RXD2 After R.E. CLK 0 tRST 43 Reset time Reset active to reset end 4Tclk Input Signals Input Pulse Width 1*Tclk+13 USART Input Signals tIs 39 Input setup time RXDn (asynchronous mode) Before R.E. CLK 12 tIh 39 Input hold time RXDn (asynchronous mode) After R.E. CLK 0 tCLKX 40 CKXn input period (synchronous mode) 200 tRXS 40 RDXn setup time (synchronous mode) Before F.E. CKX in synchronous mode 4 tRXH 40 RDXn hold time (synchronous mode) After F.E. CKX in synchronous mode 2 MICROWIRE / SPI Input Signals tMSKh 42 MICROWIRE Clock High At 2.0V (both edges) 80 tMSKl 42 MICROWIRE Clock Low At 0.8V (both edges) 80 tMSKp 42 MICROWIRE Clock Period MnIDL bit = 0; R.E. MSK to next R.E. MSK 200 43 MIDL bit = 1; F.E. MSK to next F.E. MSK tMSKh 42 MSK Hold (slave only) After MCS becomes inactive 40 tMSKs 42 MSK Setup (slave only) Before MCS becomes active 80 tMCSh 42 MCS Hold (slave only) MIDL bit = 0: After F.E. MSK 40 43 MIDL bit = 1: After R.E. MSK tMCSs 42 MCS Setup (slave only) MIDL bit = 0: Before R.E. MSK 80 43 MIDL bit = 1: Before F.E. MSK tMDIh 42 MICROWIRE Data In Hold (master) Normal Mode: After R.E. MSK 0 44 Alternate Mode: After F.E. MSK 42 MICROWIRE Data In Hold (slave) Normal Mode: After R.E. MSK 40 44 Alternate Mode: After F.E. MSK tMDIs 42 MICROWIRE Data In Setup Normal Mode: Before R.E. MSK 80 44 Alternate Mode: Before F.E. MSK Multi-Function Timer Input Signals tTAH 47 TnA High Time R.E. CLK TCLK+5 tTAL 47 TnA Low Time R.E. CLK TCLK+5 tTBH 47 TnB High Time R.E. CLK TCLK+5 tTBL 47 TnB Low Time R.E. CLK TCLK+5 a. Only when operating with an external square wave on X2CKI; otherwise a 32 kHz crystal network must be used between X2CKI and X2CKO. If the slow clock is internally generated from the fast clock, it may not exceed this given limit. Table 24 Input Signal Requirements Symbol Figure Description Reference Min (ns) Max (ns) CR16MNS5, CR16MFS5, and CR16MPS5 are Obsolete Devices |
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