6MPS5 datasheet(73/101 Pages) TI1

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18.1.2

Single Channel, Continuous Conversion Mode

In the single channel, continuous conversion mode, the A/D

Converter performs conversions repeatedly using the same

specified channel.

The software starts a conversion sequence by setting the

START bit. The A/D Converter performs four A/D conver-

sions in sequence using the same channel, pausing only for

the programmable sampling delay time used in all conver-

sion operations. It loads the four results into the A/D data reg-

isters in sequence, starting with ADDATA0 and ending with

ADDATA3. After it loads all four registers, it sets the EOC

(end of conversion) bit. If the A/D Converter interrupt is en-

abled, an interrupt to the CPU is generated at this time.

The START bit remains set until cleared by the software. If

the software does not clear the START bit, the A/D Converter

continues performing conversions using the same input

channel, storing the results in ADDATA0 following ADDATA3.

To prevent an overrun error, the software must read the re-

sults from the data registers before the A/D Converter writes

the next result into ADDATA0 following ADDATA3.

When the software clears the START bit, the A/D Converter

first completes the conversion currently in progress, then

stops and sets the EOC bit. A 2-bit buffer pointer in the

ADCST register points to the register containing the final re-

sult.

18.1.3

4-Channel Scan, Single Conversion Mode

In the 4-channel scan, single conversion mode, the A/D Con-

verter performs four conversions using four adjacent input

channels.

The software starts the conversion sequence by setting the

START bit. The A/D Converter performs four A/D conver-

sions in sequence using four adjacent channels, starting with

the specified channel and pausing only for the programmable

sampling delay time. It loads the four results into the A/D data

registers in sequence, starting with ADDATA0 and ending

with ADDATA3. After it loads all four registers, it clears the

START bit and sets the EOC (end of conversion) bit. If the A/

D Converter interrupt is enabled, an interrupt to the CPU is

generated at this time.

18.1.4

Channel Scan, Continuous Conversion Mode

In the 4-channel scan, continuous conversion mode, the A/D

Converter performs conversions repeatedly using four adja-

cent input channels.

The software starts conversion operations by setting the

START bit. The A/D Converter performs four A/D conver-

sions in sequence using four adjacent channels, starting with

the specified channel and pausing only for the programmable

sampling delay time. It loads the four results into the A/D data

registers in sequence, starting with ADDATA0 and ending

with ADDATA3. After it loads all four registers, it sets the EOC

(end of conversion) bit. If the A/D Converter interrupt is en-

abled, an interrupt to the CPU is generated at this time.

The START bit remains set until cleared by the software. If

the software does not clear the START bit, the A/D Converter

continues performing conversions, repeating the same se-

quence using the same four input channels and the same se-

quence of data registers. To prevent an overrun error, the

software must read the results from the data registers before

the A/D Converter writes the next result into ADDATA0.

When the software clears the START bit, the A/D Converter

first completes the 4-channel conversion sequence currently

in progress, then stops and sets the EOC bit.

18.2

A/D CONVERTER REGISTERS

The software controls the A/D Converter and reads the A/D

results by accessing the ADC registers. There are eight such

registers:

•

ADC Status Register (ADCST)

•

ADC Control 1 Register (ADCCNT1)

•

ADC Control 2 Register (ADCCNT2)

•

ADC Control 3 Register (ADCCNT3)

•

ADC Data Registers (ADDATA0 through ADDATA3)

18.2.1

ADC Status Register (ADCST)

The ADCST register is a byte-wide register that indicates the

current status of the A/D Converter. One bit in this register,

the OVF flag bit, is cleared by writing a 1 to its bit position.

The other bits are read-only bits, so the values written to

them are ignored. Upon reset, the register is set to 30 hex.

The register format is shown below.

EOC

End of Conversion. This read-only bit reports

the status of the most recent A/D Converter op-

eration. When cleared to 0, it indicates that the

conversion is not complete. When set to 1, it in-

dicates that the conversion is complete. The

hardware sets this bit when it places the con-

version results in the buffer and clears it when

any of the data registers are read.

BUSY

ADC Busy. This read-only bit is set to 1 when

the A/D Converter is busy converting data and

is cleared to 0 when the A/D Converter is idle

or disabled.

OVF

Overflow. The hardware sets this bit to 1 when

the A/D Converter finishes a conversion and at-

tempts to store the results in one of the data

registers (ADDATA0-ADDATA3) while the reg-

ister is full. When this happens, the A/D Con-

verter overwrites the data in the data register,

sets the OVF flag, and continues operating.

The OVF flag remains set until cleared by the

software. The software clears the flag by writ-

ing a 1 to it. Writing a 0 to this bit has no effect.

BUFPTR

Buffer Pointer. This 2-bit, read-only field identi-

fies the data register that was most recently

written with new data:

00 = ADDATA0

01 = ADDATA1

10 = ADDATA2

11 = ADDATA3

This register is initialized to 11 when a new con-

version is started (when ADCCNT2.START is

changed from 0 to 1) and is automatically incre-

mented every time a result is written to buffers

ADDATA0-ADDATA3. The result is a four-entry

Reserved

BUFPTR

Reserved

OVF

BUSY

EOC

CR16MNS5, CR16MFS5, and CR16MPS5 are Obsolete Devices

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