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9.0

Interrupts

The Interrupt Control Unit (ICU) receives interrupt requests

from internal and external sources and generates interrupts

to the CPU. Interrupts from the timers, USARTs, MICROW-

IRE/SPI interface, Multi-Input Wake-Up, and A/D converter

are all maskable interrupts. The highest-priority interrupt is

the Non-Maskable Interrupt (NMI), which is triggered by a

falling edge received on the NMI input pin. The NMI pin is not

available on the 44-pin packages.

9.1

INTERRUPT OPERATION

An exception is an event that temporarily stops the normal

flow of program execution and causes execution of a sepa-

rate service routine. Upon completion of the service routine,

execution of the interrupted program continues from the point

at which it was stopped.

There are two kinds of exceptions, called traps and inter-

rupts. A trap is the result of some action or condition in the

program itself, such as execution of an Exception (EXCP) in-

struction. An interrupt is a CPU-external event, such as a sig-

nal received on a Multi-Input Wake-Up input or a request

from an on-chip peripheral module for service.

The operation of traps is beyond the scope of this data sheet.

For information on traps, and for additional detailed informa-

tion on interrupts not provided in this data sheet, please refer

to the CompactRISC CR16B Programmer's Reference Man-

ual.

9.1.1

Interrupt Operation Summary

When an interrupt occurs, the on-chip hardware performs the

following steps:

1. Decrements the Interrupt Stack Point (ISP) by four.

2. Saves the contents of the Program Counter (PC) and

Processor Status Register (PSR) on the interrupt stack.

3. Clears the I, P, and T bits in the Processor Status Reg-

ister (PSR). These are the Global Maskable Interrupt

Enable bit, Trace Trap Pending bit, and Trace bit, re-

spectively.

4. Reads the interrupt vector from the Interrupt Vector Reg-

ister (IVCT).

5. Combines the interrupt vector with the value in the Inter-

rupt Base (INTBASE) register to obtain an address in the

Interrupt Dispatch Table, and loads the dispatch table

entry into the Program Counter (PC).

From this point onward, the CPU executes the interrupt ser-

vice routine. The service routine ends with a Return from Ex-

ception (RETX) instruction. This returns the CPU to the

interrupted program. The CPU restores the contents of the

PC and PSR registers from the stack and increments the In-

terrupt Stack Pointer by four.

9.1.2

Service Routine Addresses

When an interrupt or trap occurs, the CPU executes a service

routine. There are different service routines for different inter-

rupts and traps. Each service routine may reside anywhere

in program memory. The starting addresses of the service

routines are contained in a table called the Dispatch Table.

Entries in the table are organized in the order shown in

Table10.

Each entry in the Dispatch Table consists of two bytes that

provide bits 1 through 16 of the starting address of the corre-

sponding service routine. The full 21-bit address of a service

routine is reconstructed by adding a leading 0 and a trailing

0 to the 16-bit table entry. Because the program memory of

the device only occupies the range of 0000-BFFF hex, en-

tries in the table are restricted to this range.

The INTBASE register is a pointer to the Dispatch Table.

Upon reset, the initialization software must write the starting

address of the Dispatch Table to the INTBASE register, a 21-

bit register with the five most significant bits and the least sig-

nificant bit always equal to 0. It is typically kept in the flash

EEPROM program memory. The Dispatch Table is 32 words

long.

Table 10

Dispatch Table Entries

0: Reserved

1: NMI

2: Reserved

3: Reserved

4: Reserved

5: SVC (Supervisor Call Trap)

6: DVC (Divided by Zero Trap)

7: FLG (Flag Trap)

8: BPT (Breakpoint Trap)

9: TRC (Trace Trap)

10: UND (Undefined Instruction Trap)

11: Reserved

12: Reserved

13: Reserved

14: Reserved

15: Reserved

16: INT0 (Reserved)

17: INT1 (A/D Converter)

18: INT2 (Multi-Input Wake-Up)

19: INT3 (Reserved)

20: INT4 (USART2 Tx)

21: INT5 (USART1 Tx)

22: INT6 (MICROWIRE/SPI Rx/Tx)

23: INT7 (Reserved)

24: INT8 (USART2 Rx)

25: INT9 (USART1 Rx)

26: INT10 (Timer 2 Input B)

27: INT11 (Timer 2 Input A)

28: INT12 (Timer 1 Input B)

29: INT13 (Timer 1 Input A)

30: INT14 (Timer 0)

31: INT15 (Reserved)

CR16MNS5, CR16MFS5, and CR16MPS5 are Obsolete Devices

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