6MPS5 datasheet(49/101 Pages) TI1

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Some Power Save modes stops the system clock (the high-

frequency and/or low-frequency clock) completely. If the sys-

tem clock is stopped, the timer stops counting until the sys-

tem clock resumes operation.

In the Idle or Halt mode, the system clock stops completely,

which stops the operation of the timers. In that case, the tim-

ers stop counting until the system clock resumes operation.

14.2

TIMER OPERATING MODES

Each timer/counter unit can be configured to operate in any

of the following modes:

•

Processor-Independent Pulse Width Modulation (PWM)

mode

•

Dual Input Capture mode

•

Dual Independent Timer mode

•

Single Input Capture and Single Timer mode

Upon reset, the timers are disabled. To configure and start

the timers, the software must write a set of values to the reg-

isters that control the timers. The registers are described in

Section14.5.

14.2.1

Mode 1: Processor-Independent PWM

Mode 1 is the Processor-Independent Pulse Width Modula-

tion (PWM) mode, which generates pulses of a specified

width and duty cycle, and which also provides a separate

general-purpose timer/counter.

Figure13 is a block diagram of the Multi-Function Timer con-

figured to operate in Mode 1. Timer/Counter I (TnCNT1)

functions as the time base for the PWM timer. It counts down

at the clock rate selected for the counter. When an underflow

occurs, the timer register is reloaded alternately from the

TnCRA and TnCRB register, and counting proceeds down-

ward from the loaded value.

On the first underflow, the timer is loaded from TnCRA, then

from TnCRB on the next underflow, then from TnCRA again

on the next underflow, and so on. Every time the counter is

stopped and restarted, it always obtains its first reload value

from TnCRA. This is true whether the timer is restarted upon

reset, after entering Mode 1 from another mode, or after stop-

ping and restarting the clock with the Timer/Counter I clock

selector.

The timer can be configured to toggle the TnA output bit upon

each underflow. This generates a clock signal on TnA with

the width and duty cycle determined by the values stored in

the TnCRA and TnCRB registers. This is a “processor-inde-

pendent” PWM clock because once the timer is set up, no

more action is required from the CPU to generate a continu-

ous PWM signal.

The timer can be configured to generate separate interrupts

upon reload from TnCRA and TnCRB. The interrupts can be

enabled or disabled under software control. The CPU can de-

termine the cause of each interrupt by looking at the TnAPND

and TnBPND flags, which are set by the hardware upon each

occurrence of a timer reload.

In Mode 1, Timer/Counter II (TnCNT2) can be used either as

a simple system timer, an external event counter, or a pulse

accumulate counter. The clock counts down using the clock

selected with the Timer/Counter II clock selector. It generates

an interrupt upon each underflow if the interrupt is enabled

with the TnDIEN bit.

Figure 13.

Mode 1: Processor-Independent PWM Block Diagram

Reload A = Time 1

Timer/Counter I

Reload B = Time 2

Timer I

Clock

Underflow

TnA

TnAIEN

TnAPND

TnCNT1

TnCRA

TnCRB

TnBIEN

TnBPND

Timer

Interrupt A

Timer

Interrupt B

TnAEN

Timer/Counter II

TnCNT2

Timer II

Clock

TnDIEN

TnDPND

Timer

Interrupt D

TnB

Clock

Selector

Underflow

CR16MNS5, CR16MFS5, and CR16MPS5 are Obsolete Devices

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