6MPS5 datasheet(38/101 Pages) TI1

38 / 101 page

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11.0

Dual Clock and Reset

The Dual Clock and Reset module (CLK2RES) generates a

high-speed main system clock from an external crystal net-

work and a slow clock (32.768 kHz or other rate) for operat-

ing the device in Power Save mode. It also provides the main

system reset signal and a power-on reset function.

Figure6 is block diagram of the Dual Clock and Reset mod-

ule.

11.1

EXTERNAL CRYSTAL NETWORK

An external crystal network is required at pins X1CKI and

X1CKO for the main clock. A similar external crystal network

may be used at pins X2CKI and X2CKO for the slow clock in

packages that have these pins. If an external crystal network

is not used for the slow clock, the clock is generated by divid-

ing the fast main clock.

Figure7 shows the required crystal network at X1CKI/

X1CKO and optional crystal network at X2CKI/X2CKO.

Table13 shows the component specifications for the main

crystal network and Table14 shows the component specifi-

cations for the 32.768 kHz crystal network.

Figure 6.

Dual Clock and Reset Module Block Diagram

14-Bit Timer

6-Bit Timer

Start-Up-Delay

Preset

Power-On-Reset

System

Reset

Stop

Main Osc In

RESET

X1CKI

X1CKO

X2CKI

X2CKO

Main Osc.

32kHz Osc.

Stop Main Osc.

Stop 32kHz Osc.

Main Clk

Good Main

Clk

Low Speed

Clk

Good Low

Speed Clk

Stop Low

Speed Clk

Time-out

8-Bit

Prescaler

Div.

by-2

Figure 7.

External Crystal Network

X1CKI / X2CKI

X1CKO / X2CKO

XTAL

CR16MNS5, CR16MFS5, and CR16MPS5 are Obsolete Devices

6MPS5 Datasheet(PDF) 38 Page - Texas Instruments

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