Z8018233FSC datasheet(71/109 Pages) ZILOG

71 / 109 page

3-71

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

Bits 3-1 Interrupt ID Bits

This 3-bit field is used to determine the highest priority

interrupt pending (see Table 19).

Bit 0 Interrupt Pending

This bit is logic 0 and interrupt is pending.

When the PC accesses the IIR, the contents of the register

and all pending interrupts are frozen. Any new interrupts

will be recorded, but not acknowledged, during the IIR

access.

Although this bit is disabled by default, it is advised that

this bit is enabled to prevent interrupt conflict between

MIMIC and ESCC interrupts.

000000

Interrupt ID bit (2)

Always '0'

FIFO Enabled Flag

Interrupt ID bit (1)

Interrupt ID bit (0)

0 if Interrupt Pending

Figure 73. Interrupt Identification Register

(PC Read Only, Address 02H)

(Z180 MPU no access)

Interrupt Identification Register

Bit 7 and Bit 6 FIFO’s Enabled

These bits will read 1 if the FIFO mode is enabled on the

MIMIC.

Bit 5 and Bit 4 Always Read 0

Reserved bits.

000000

Framing Error

Break Interrupt

THRE

TEMT

Error in RCVR FIFO

Parity Error

Overrun Error

Data Ready

Figure 74. Line Status Register

(PC Read Only, Address 05H)

(Z180 MPU Read/Write bits 6, 4, 3, 2, Address xxF5H)

Table 19. Interrupt Identification Field

Priority

Interrupt Source

INT Reset Control

Highest

Overrun, Parity, Framing error

Read Line Status Register

or Break detect bits set by MPU

2nd

Received Data trigger level

RCVR FIFO drops below trigger level

2nd

Receiver Timeout with data

Read RCVR FIFO

in RCVR FIFO.

3rd

Transmitter Holding

Writing to the Transmitter Holding

Identification Register when the

THRE is the source of the interrupt.

4th

MODEM status: CTS,

Reading the MODEM

DSR, RI or DCD

status register.

Z8018233FSC Datasheet(PDF) 71 Page - Zilog, Inc.

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