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Z8018233FSC Datasheet(PDF) 75 Page - Zilog, Inc.

No. de pieza Z8018233FSC
Descripción Electrónicos  ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP??
PDF  109 Pages
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Fabricante Electrónico  ZILOG [Zilog, Inc.]
Página de inicio  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8018233FSC Datasheet(HTML) 75 Page - Zilog, Inc.

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Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
PRELIMINARY
Zilog
DS971820600
Z80182 ENHANCEMENTS REGISTER
Bit <7-6> Reserved
Bit 5 Force Z180 Halt Mode
If this bit is set to 1, it disables the 16 cycle halt recovery
and halt control over the busses and pins. This bit is used
to allow DMA and Refresh Access to take place during halt
(like Z180). This bit is set to 0 on reset.
Bit 4 TxDA Tri-state
The TxDA pin can be tri-stated on assertion of the /HALT
pin. This prevents the TxDA from driving and external
device when /HALT output is used to force other devices
into power-down modes. This feature is disabled on power-
up or reset. It is also controlled by bit 5 in the enhancement
register, this feature is disabled if bit 5 is set.
Bit 3 ESCC Clock Divider
The ESCC clock can be provided with the Z180 core's PHI
clock or by a PHI clock divide by 2 circuit. When this bit is
set, the ESCC's clock will be Z180's PHI clock divided by
two. Upon power-up or reset, the ESCC clock frequency is
equal to the Z180 core's PHI clock output.
Note: If operating above 20 MHz/5V or 10 MHz/3V, this bit
should be set for ESCC divide-by-two mode.
0
0
0
0000
0
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
ESCC Clock Divider
TxDA Tri-state
Force Z180 Halt mode
Reserved
Figure 82. Z80182 Enhancements Register
(Z180 MPU Read/Write, Address xxD9H)



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