Z8018233FSC datasheet(11/109 Pages) ZILOG

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Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

MULTIPLEXED PIN DESCRIPTIONS

A18/T

OUT. During Reset, this pin is initialized as an A18 pin.

If either TOC1 or TOC0 bit of the Timer Control Register

(TCR) is set to 1, The T

OUT function is selected. If TOC1 and

TOC0 bits are cleared to 0, the A18 function is selected.

In normal user mode (on-chip bus master), the A18 signal

for the chip select logic is obtained from the CPU before

the external pin is muxed as A18/T

OUT. Therefore, the

selection of T

OUT will not affect the operation of the 182 chip

select logic. However, in adapter mode (off-chip bus

master), the A18 signal MUST be provided by the external

bus master.

CKA0//DREQ0. During Reset, this pin is initialized as

CKA0 pin. If either DM1 or SM1 in the DMA Mode Register

(DMODE) is set to 1, /DREQ0 function is always selected.

CKA1//TEND0. During Reset, this pin is initialized as

CKA1 pin. If CKA1D bit in the ASCI control register

Ch1(CNTLA1) is set to 1, /TEND0 function is selected. If

CKA1D bit is set to 0, CKA1 function is selected.

RxS//CTS1. During Reset, this pin is initialized as the RxS

pin. If CTS1E bit in the ASCI status register Ch1 (STAT1) is

set to 1, /CTS1 function is selected. If CTS1E bit is set to 0,

RxS function is selected. This pin is also multiplexed with

PB7 based on bit 6 in the System Configuration Register.

The pins below are triple-multiplexed based upon the

values of bit 1 and bit 2 of the System Configuration

Reset, both bits 1 and 2 are 0, so /TEND1,TxS,CKS are

selected.

Table 2. Triple Multiplexed Pins

Bit 1

Bit 2

Master Configuration Register

/TEND1,TxS,CKS

/RTSB,/DTR//REQB,/W//REQB

/TEND1,TxS,CKS

/HRxRDY,//HTxRDY,HINTR

The pins below are multiplexed based upon the value of bit

1 of the System Configuration register. If bit 1 is 0, then the

Z80182/Z8L182 Mode 0 (non-16550 MIMIC mode) signals

are selected; if bit 1 is 1, then Z80182/Z8L182 Mode 1

(16550 MIMIC mode) signals are selected. On Reset,

Z80182/Z8L182 Mode 0 is always selected as shown in

Table 3.

Table 3. Mode 0 and Mode 1 Multiplexed Pins

Z80182/Z8L182

Mode 0

Mode 1

TxDB

/HDDIS

RxDB

HA1

/TRxCB

HA0

/RTxCB

HA2

/SYNCB

/HCS

/CTSB

/HWR

/DCDB

/HRD

PA7-PA0

HD7-HD0

Z8018233FSC Datasheet(PDF) 11 Page - Zilog, Inc.

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