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Z8018233FSC Datasheet(PDF) 44 Page - Zilog, Inc. |
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Z8018233FSC Datasheet(HTML) 44 Page - Zilog, Inc. |
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44 / 109 page ![]() 3-44 Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL PRELIMINARY Zilog DS971820600 SYSTEM CONTROL REGISTERS (Continued) M1E /M1TE -- - 11 1 11 111 R/W I/O Compatibility Addr 3EH Bit Upon Reset - - /M1 Temporary Enable /M1 Enable /IOC OMCR W R/W R/W Note: This register should be programmed to 0x0xxxxxb (x = don't care) as a part of Initialization. Figure 49. Operation Mode Control Register IOA7 IOA6 --- 00 0 11 111 R/W I/O Stop Addr 3FH Bit Upon Reset - - I/O Address Combination of 11 is reserved IOSTP ICR R/W R/W R/W Figure 50. I/O Control Register |
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