Z8018233FSC datasheet(22/109 Pages) ZILOG

22 / 109 page

3-22

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

16550 MIMIC FIFO DESCRIPTION

The receiver FIFO consists of a 16-word FIFO capable of

storing eight data bits and three error bits for each character

stored (Figure 7). Parity error, Framing error and Break

detect bits are stored along with the data bits by copying

their value from three shadow bits that are Write Only bits

for the Z80180 MPU LSR address. The three shadow bits

are cleared after they are copied to the FIFO memory. In

FIFO mode, to write error bits into the receiver FIFO, the

MPU must first write the Parity, Framing and Break detect

status to the Line Status Register (shadow bits) and then

write the character associated into the receiver buffer. The

data and error bits will then move into the same address in

the FIFO. The error bits become available to the PC side of

the interface when that particular location becomes the

next address to read (top of FIFO). At that time, they may

either be read by the PC by accessing them in the LSR, or

they may cause an interrupt to the PC interface if so

enabled. The error bits are set by the error status of the byte

at the top of the FIFO, but may only be cleared by reading

the LSR. If successive reads of the receiver FIFO are

performed without reading the LSR, the status bits will be

set if any of the bytes read have the respective error bit set.

See Table 6 for the setting and clearing of the Line Status

16x8

Data Bits

16x3

Error

Bits

Write

Pointer

ALU

Read

Pointer

Sync

Internal Clock

MPU

CNTL

Line

PC Read

LSR

B2-B4

error

MPU Write

LSR Shadow

B2-B4

MPU

Databus

(MPU Side Write)

Internal Clock

MPU

IRQ

Sync

PC Side

Databus

(PC Side Read)

FIFO Control

IRQ

Cntrl

Line

Internal Clock

MPU Side

Interface

16550

MIMIC or

PC Side

Interface

Figure 7. 16550 MIMIC Receiver FIFO Block Diagram

Z8018233FSC Datasheet(PDF) 22 Page - Zilog, Inc.

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