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Z8018233FSC Datasheet(PDF) 19 Page - Zilog, Inc. |
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Z8018233FSC Datasheet(HTML) 19 Page - Zilog, Inc. |
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19 / 109 page ![]() 3-19 Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL PRELIMINARY Zilog DS971820600 s NRZ, NRZI or FM encoding/decoding. Manchester Code Decoding (Encoding with External Logic). s Baud Rate Generator in each Channel s Digital Phase-Locked Loop (DPLL) for Clock Recovery s Crystal Oscillator The following features are implemented in the ESCC™ for the Z80182/Z8L182 only: s New 32-bit CRC-32 (Ethernet Polynomial) s ESCC Programmable Clock - programmed to be equal to system clock divided by one or two - programmed by Z80182 Enhancement Register Note: The ESCC™ programmable clock must be programmed to divide-by-two mode when operating above the following conditions: – PHI > 20 MHz at 5.0V – PHI > 10 MHz at 3.0V The following features are common to both the ESCC and the CMOS SCC: s Two independent full-duplex channels s Synchronous/Isochronous data rates: - Up to 1/4 of the PCLK using external clock source - Up to 5 Mbits/sec at 20 MHz PCLK (ESCC). s Asynchronous capabilities - 5, 6, 7 or 8 bits/character (capable of handling 4 bits/character or less) - 1, 1.5, or 2 stop bits - Odd or even parity - Times 1, 16, 32 or 64 clock modes - Break generation and detection - Parity, overrun and framing error detection s Byte oriented synchronous capabilities: - Internal or external character synchronization - One or two sync characters (6 or 8 bits/sync character) in separate registers - Automatic Cyclic Redundancy Check (CRC) generation/detection s SDLC/HDLC capabilities: - Abort sequence generation and checking - Automatic zero insertion and detection - Automatic flag insertion between messages - Address field recognition - I-field residue handling - CRC generation/detection - SDLC loop mode with EOP recognition/loop entry and exit |
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