Z8018233FSC datasheet(12/109 Pages) ZILOG

12 / 109 page

3-12

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

Ports B and C Multiplexed Pin Descriptions

Ports B and C are pin multiplexed with the Z180 ASCI

functions and part of ESCC channel A. The MUX function

is controlled by bits 7-5 in the System Configuration Register.

The MUX is organized as shown in Table 4.

Table 4. Multiplexed Port Pins

Port Mode

ASCI/ESCC Mode

Function

PB7

RxS,/CTS1

PB6 Select with bit 6=1

RxA1

PB5 System Config Reg.

TxA1

PB4

RxA0

PB3

TxA0

PB2 Select with bit 5=1

/DCD0

PB1 System Config Reg.

/CTS0 (Note 1)

PB0

/RTS0

PC7

Always Reads /INT2 Ext.

Status

PC6

Always Reads /INT1 Ext.

Status

PC5

/W//REQA

PC4

/SYNCA

PC3 Select with bit 7=1

/DTR//REQA

PC2 System Config Reg.

/RTSA (Note 2)

PC1

/CTSA

PC0

/DCDA

Note 1:

When the Port function (PB1) is selected, the internal Z180/

CTS0 is always driven Low. This ensures that the ASCI

channel 0 of the Z180™ MPU is enabled to transmit data.

Note 2:

Interrupt Edge /Pin MUX register, bit 3 chooses between

the /MWR or PC2//RTSA combination; the System

Configuration Register bit 7 chooses between PC2 and

/RTSA.

Refer to Table 5 for the 1st, 2nd and 3rd pin functions.

Z8018233FSC Datasheet(PDF) 12 Page - Zilog, Inc.

Z8018233FSC Datasheet(HTML) 12 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL