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LTC2421/LTC2422

24212f

resistance ground plane through a minimum length trace.

The use of multiple via holes is recommended to further

reduce the connection resistance.

In an alternative configuration, the GND pin of the con-

verter can be the single-point-ground in a single point

grounding system. The input signal ground, the reference

signal ground, the digital drivers ground (usually the digi-

tal ground) and the power supply ground (the analog

ground) should be connected in a star configuration with

the common point located as close to the GND pin as

possible.

The power supply current during the conversion state

should be kept to a minimum. This is achieved by restrict-

ing the number of digital signal transitions occurring dur-

ing this period.

While a digital input signal is in the range 0.5V to

(VCC – 0.5V), the CMOS input receiver draws additional

current from the power supply. It should be noted that,

when any one of the digital input signals (FO, CS and SCK

in External SCK mode of operation) is within this range, the

LTC2421/LTC2422 power supply current may increase

even if the signal in question is at a valid logic level. For

micropower operation and in order to minimize the poten-

tial errors due to additional ground pin current, it is recom-

mended to drive all digital input signals to full CMOS levels

[VIL < 0.4V and VOH > (VCC – 0.4V)].

Severe ground pin current disturbances can also occur

due to the undershoot of fast digital input signals. Under-

shoot and overshoot can occur because of the imped-

ance mismatch at the converter pin when the transition

time of an external control signal is less than twice the

propagation delay from the driver to LTC2421/LTC2422.

For reference, on a regular FR-4 board, signal propaga-

tion velocity is approximately 183ps/inch for internal

traces and 170ps/inch for surface traces. Thus, a driver

generating a control signal with a minimum transition

time of 1ns must be connected to the converter pin through

a trace shorter than 2.5 inches. This problem becomes

particularly difficult when shared control lines are used

and multiple reflections may occur. The solution is to

carefully terminate all transmission lines close to their

characteristic impedance.

APPLICATIO S I FOR ATIO

Parallel termination near the LTC2421/LTC2422 pin will

eliminate this problem but will increase the driver power

dissipation. A series resistor between 27

Ωand56Ωplaced

near the driver or near the LTC2421/LTC2422 pin will also

eliminate this problem without additional power dissipa-

tion. The actual resistor value depends upon the trace

impedance and connection topology.

Driving the Input and Reference

The analog input and reference of the typical delta-sigma

analog-to-digital converter are applied to a switched ca-

pacitor network. This network consists of capacitors switch-

ing between the analog input (VIN), ZSSET(Pin 5) and FSSET

(Pin 2). The result is small current spikes seen at both VIN

and VREF. A simplified input equivalent circuit is shown in

Figure 16.

The key to understanding the effects of this dynamic input

current is based on a simple first order RC time constant

model. Using the internal oscillator, the LTC2421/

LTC2422’s internal switched capacitor network is clocked

at 153,600Hz corresponding to a 6.5

µs sampling period.

Fourteen time constants are required each time a capacitor

is switched in order to achieve 1ppm settling accuracy.

Therefore, the equivalent time constant at VIN and VREF

should be less than 6.5

µs/14 = 460ns in order to achieve

1ppm accuracy.

Figure 16. LTC2421/LTC2422 Equivalent Analog Input Circuit

VREF

VIN

VCC

RSW

AVERAGE INPUT CURRENT:

IIN = 0.25(VIN – 0.5 • VREF)fCEQ

IREF(LEAK)

VCC

RSW

CEQ

1pF (TYP)

RSW

IIN(LEAK)

IIN

24212 F16

IIN(LEAK)

SWITCHING FREQUENCY

f = 153.6kHz FOR INTERNAL OSCILLATOR (fO = LOGIC LOW OR HIGH)

f = fEOSC FOR EXTERNAL OSCILLATORS

GND

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