LTC2421_15 datasheet(18/32 Pages) LINER

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LTC2421/LTC2422

24212f

APPLICATIO S I FOR ATIO

HIGH before the first rising edge of SCK. In the internal

SCK timing mode, SCK goes HIGH and the device begins

outputting data at time tEOCtest after the falling edge of CS

(if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW

during the falling edge of EOC). The value of tEOCtest is 23µs

if the device is using its internal oscillator (F0 = logic LOW

or HIGH). If FO is driven by an external oscillator of fre-

quency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled

HIGH before time tEOCtest, the device remains in the sleep

state. The conversion result is held in the internal static

shift register.

If CS remains LOW longer than tEOCtest, the first rising

edge of SCK will occur and the conversion result is serially

shifted out of the SDO pin. The data output cycle begins on

this first rising edge of SCK and concludes after the 24th

rising edge. Data is shifted out the SDO pin on each falling

edge of SCK. The internally generated serial clock is output

to the SCK pin. This signal may be used to shift the con-

version result into external circuitry. EOC can be latched

on the first rising edge of SCK and the last bit of the con-

version result on the 24th rising edge of SCK. After the

24th rising edge, SDO goes HIGH (EOC = 1), SCK stays

HIGH, and a new conversion starts.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first and 24th rising edge of

SCK, see Figure 10. On the rising edge of CS, the device

aborts the data output state and immediately initiates a

new conversion. This is useful for systems not requiring

all 24 bits of output data, aborting an invalid conversion

cycle, or synchronizing the start of a conversion. If CS is

pulled HIGH while the converter is driving SCK LOW, the

internal pull-up is not available to restore SCK to a logic

HIGH state. This will cause the device to exit the internal

serial clock mode on the next falling edge of CS. This can

be avoided by adding an external 10k pull-up resistor to

the SCK pin or by never pulling CS HIGH when SCK is LOW.

Whenever SCK is LOW, the LTC2421/LTC2422’s internal

pull-up at pin SCK is disabled. Normally, SCK is not exter-

nally driven if the device is in the internal SCK timing mode.

However, certain applications may require an external driver

on SCK. If this driver goes Hi-Z after outputting a LOW

signal, the LTC2421/LTC2422’s internal pull-up remains

disabled. Hence, SCK remains LOW. On the next falling

edge of CS, the device is switched to the external SCK

timing mode. By adding an external 10k pull-up resistor to

SCK, this pin goes HIGH once the external driver goes

Hi-Z. On the next CS falling edge, the device will remain in

the internal SCK timing mode.

Figure 9. Internal Serial Clock, Single Cycle Operation

VCC

10k

VCC

FSSET

ZSSET

SCK

CH1

SDO

GND

REFERENCE VOLTAGE

ZSSET + 0.1V TO VCC

0V TO FSSET – 100mV

CH0

= INTERNAL OSC/50Hz REJECTION

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

µF

110

2.7V TO 5.5V

LTC2422

VCC

ANALOG INPUT RANGE

ZSSET – 0.12VREF TO

FSSET + 0.12VREF

(VREF = FSSET – ZSSET)

SDO

SCK

(INTERNAL)

MSB

EXR

SIG

BIT 0

LSB20

BIT 4

TEST EOC

BIT 19

BIT 18

BIT 20

BIT 21

BIT 22

EOC

CH0/CH1

BIT 23

SLEEP

DATA OUTPUT

CONVERSION

24212 F09

<tEOCtest

Hi-Z

TEST EOC

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