LTC2421_15 datasheet(14/32 Pages) LINER

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LTC2421/LTC2422

24212f

external serial clock. If the change occurs during the con-

version state, the result of the conversion in progress may

be outside specifications but the following conversions

will not be affected. If the change occurs during the data

output state and the converter is in the Internal SCK mode,

the serial clock duty cycle may be affected but the serial

data stream will remain valid.

Table 3 summarizes the duration of each state as a func-

tion of FO.

SERIAL INTERFACE

The LTC2421/LTC2422 transmit the conversion results

and receives the start of conversion command through a

synchronous 3-wire interface. During the conversion and

sleep states, this interface can be used to assess the con-

verter status and during the data output state, it is used to

read the conversion result.

Serial Clock Input/Output (SCK)

The serial clock signal present on SCK (Pin 9) is used to

synchronize the data transfer. Each bit of data is shifted out

the SDO pin on the falling edge of the serial clock.

In the Internal SCK mode of operation, the SCK pin is an

output and the LTC2421/LTC2422 create their own serial

clock by dividing the internal conversion clock by 8. In the

External SCK mode of operation, the SCK pin is used as

input. The internal or external SCK mode is selected on

power-up and then reselected every time a HIGH-to-LOW

transition is detected at the CS pin. If SCK is HIGH or

floating at power-up or during this transition, the con-

verter enters the internal SCK mode. If SCK is LOW at

power-up or during this transition, the converter enters

the external SCK mode.

Serial Data Output (SDO)

The serial data output pin, SDO (Pin 8), drives the serial

data during the data output state. In addition, the SDO pin

is used as an end of conversion indicator during the con-

version and sleep states.

When CS (Pin 7) is HIGH, the SDO driver is switched to a

high impedance state. This allows sharing the serial

Table 3. LTC2421/LTC2422 State Duration

State

Operating Mode

Duration

CONVERT

Internal Oscillator

FO = LOW

133ms

(60Hz Rejection)

FO = HIGH

160ms

(50Hz Rejection)

External Oscillator

FO = External Oscillator

20510/fEOSCs

with Frequency fEOSC kHz

(fEOSC/2560 Rejection)

SLEEP

As Long As CS = HIGH Until CS = 0 and SCK

DATA OUTPUT

Internal Serial Clock

FO = LOW/HIGH

As Long As CS = LOW But Not Longer Than 1.28ms

(Internal Oscillator)

(24 SCK cycles)

FO = External Oscillator with

As Long As CS = LOW But Not Longer Than 192/fEOSCms

Frequency fEOSC kHz

(24 SCK cycles)

External Serial Clock with

As Long As CS = LOW But Not Longer Than 24/fSCKms

Frequency fSCK kHz

(24 SCK cycles)

APPLICATIO S I FOR ATIO

Figure 5. LTC2421/LTC2422 Normal Mode Rejection When

Using an External Oscillator of Frequency fEOSC

INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)

–12

–8

–4

048

24212 F05

–60

–70

–80

–90

–100

–110

–120

–130

–140

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