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LTC2421 Datasheet(PDF) 16 Page - Linear Technology

No. de pieza LTC2421
Descripción Electrónicos  1-/2-Channel 20-Bit Power No Latency ADCs in MSOP-10
PDF  32 Pages
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Fabricante Electrónico  LINER [Linear Technology]
Página de inicio  http://www.linear.com
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LTC2421 Datasheet(HTML) 16 Page - Linear Technology

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LTC2421/LTC2422
24212f
APPLICATIO S I FOR ATIO
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
Figure 6. External Serial Clock, Single Cycle Operation
VCC
FO
FSSET
ZSSET
SCK
CH1
SDO
GND
CS
REFERENCE VOLTAGE
ZSSET + 0.1V TO VCC
0V TO FSSET – 100mV
CH0
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1
µF
110
9
8
7
6
2
3
4
5
2.7V TO 5.5V
LTC2422
VCC
3-WIRE
SERIAL I/O
ANALOG INPUT RANGE
ZSSET – 0.12VREF TO
FSSET + 0.12VREF
(VREF = FSSET – ZSSET)
EOC
CH0/CH1
BIT 23
SDO
SCK
(EXTERNAL)
CS
TEST EOC
MSB
LSB20
EXR
SIG
BIT 0
BIT 4
BIT 19
BIT 18
BIT 20
BIT 21
BIT 22
SLEEP
DATA OUTPUT
CONVERSION
24212 F06
CONVERSION
Hi-Z
Hi-Z
Hi-Z
TEST EOC
TEST EOC
CS HIGH anytime between the first rising edge and the
24th falling edge of SCK, see Figure 7. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for sys-
tems not requiring all 24 bits of output data, aborting an
invalid conversion cycle or synchronizing the start of a
conversion.
Figure 7. External Serial Clock, Reduced Data Output Length
VCC
FO
FSSET
ZSSET
SCK
CH1
SDO
GND
CS
REFERENCE VOLTAGE
ZSSET + 0.1V TO VCC
0V TO FSSET – 100mV
CH0
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1
µF
110
9
8
7
6
2
3
4
5
2.7V TO 5.5V
LTC2422
VCC
3-WIRE
SERIAL I/O
ANALOG INPUT RANGE
ZSSET – 0.12VREF TO
FSSET + 0.12VREF
(VREF = FSSET – ZSSET)
SDO
SCK
(EXTERNAL)
CS
DATA OUTPUT
CONVERSION
SLEEP
SLEEP
TEST EOC
TEST EOC
DATA OUTPUT
Hi-Z
Hi-Z
Hi-Z
CONVERSION
24212 F07
MSB
EXR
SIG
BIT 8
BIT 19
BIT 9
BIT 20
BIT 21
BIT 22
EOC
CH0/CH1
BIT 23
BIT 0
EOC
Hi-Z
TEST EOC



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