LTC2421_15 datasheet(10/32 Pages) LINER

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LTC2421/LTC2422

24212f

APPLICATIO S I FOR ATIO

The LTC2421/LTC2422 are pin compatible with the

LTC2401/LTC2402. The devices are designed to allow the

user to incorporate either device in the same design with

no modifications. While the LTC2421/LTC2422 output word

length is 24 bits (as opposed to the 32-bit output of the

LTC2401/LTC2402), its output clock timing can be identi-

cal to the LTC2401/LTC2402. As shown in Figure 1, the

LTC2421/LTC2422 data output is concluded on the falling

edge of the 24th serial clock (SCK). In order to maintain

drop-in compatibility with the LTC2401/LTC2402, it is

possible to clock the LTC2421/LTC2422 with an additional

8 serial clock pulses. This results in 8 additional output bits

which are always logic HIGH.

Converter Operation Cycle

The LTC2421/LTC2422 are low power, delta-sigma ana-

log-to-digital converters with an easy to use 3-wire serial

interface. Their operation is simple and made up of three

states. The converter operating cycle begins with the con-

version, followed by the sleep state and concluded with the

data output (see Figure 2). The 3-wire interface consists of

serial data output (SDO), a serial clock (SCK) and a chip

select (CS).

Initially, the LTC2421/LTC2422 perform a conversion. Once

the conversion is complete, the device enters the sleep

state. While in this sleep state, power consumption is re-

duced by an order of magnitude if CS is HIGH. The part

remains in the sleep state as long as CS is logic HIGH. The

conversion result is held indefinitely in a static shift regis-

ter while the converter is in the sleep state.

Figure 1. LTC2421/LTC2422 Compatible Timing with the LTC2401/LTC2402

SCK

SDO

CONVERSION

SLEEP

8 (OPTIONAL)

EOC = 1

LAST 8 BITS ALWAYS 1

EOC = 0

DATA OUT

4 STATUS BITS 20 DATA BITS

DATA OUTPUT

24212 F01

CONVERSION

CONVERT

SLEEP

DATA OUTPUT

24212 F02

CS AND

SCK

Figure 2. LTC2421/LTC2422 State Transition Diagram

Once CS is pulled LOW and SCK rising edge is applied, the

device begins outputting the conversion result. There is no

latency in the conversion result. The data output corre-

sponds to the conversion just performed. This result is

shifted out on the serial data out pin (SDO) under the

control of the serial clock (SCK). Data is updated on the

falling edge of SCK allowing the user to reliably latch data

on the rising edge of SCK, see Figure 4. The data output

state is concluded once 24 bits are read out of the ADC or

when CS is brought HIGH. The device automatically

initiates a new conversion and the cycle repeats.

Through timing control of the CS and SCK pins, the

LTC2421/LTC2422 offer several flexible modes of opera-

tion (internal or external SCK and free-running conver-

sion modes). These various modes do not require

programming configuration registers; moreover, they do

not disturb the cyclic operation described above. These

modes of operation are described in detail in the Serial

Interface Timing Modes section.

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