ADP5050ACPZ-R7 datasheet(12/60 Pages) AD

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ADP5050

Data Sheet

Rev. 0 | Page 12 of 60

Pin No.

Mnemonic

Description

PGND

Power Ground for Channel 1 and Channel 2.

DL1

Low-Side FET Gate Driver for Channel 1. Connect a resistor from this pin to ground to program the current-limit

threshold for Channel 1.

BST1

High-Side FET Driver Power Supply for Channel 1.

33, 34

SW1

Switching Node Output for Channel 1.

35, 36

PVIN1

Power Input for the Internal 5.1 V VREG Linear Regulator and the Channel 1 Buck Regulator. Connect a bypass

capacitor between this pin and ground.

EN1

Enable Input for Channel 1. An external resistor divider can be used to set the turn-on threshold.

SS12

Connect a resistor divider from this pin to VREG and ground to configure the soft start time for Channel 1 and

Channel 2 (see the Soft Start section). This pin is also used to configure parallel operation of Channel 1 and

Channel 2 (see the Parallel Operation section).

COMP1

Error Amplifier Output for Channel 1. Connect an RC network from this pin to ground.

FB1

Feedback Sensing Input for Channel 1.

Connect a resistor from RT to ground to program the switching frequency from 250 kHz to 1.4 MHz. For more

information, see the Oscillator section.

VDD

Output of the Internal 3.3 V Linear Regulator. Connect a 1 µF ceramic capacitor between this pin and ground.

SYNC/MODE

Synchronization Input/Output (SYNC). To synchronize the switching frequency of the part to an external clock,

connect this pin to an external clock with a frequency from 250 kHz to 1.4 MHz. This pin can also be configured

as a synchronization output using the I2C interface or by factory fuse.

Forced PWM or Automatic PWM/PSM Selection Pin (MODE). When this pin is logic high, each channel operates

in forced PWM or automatic PWM/PSM mode, as specified by the PSMx_ON bits in Register 6. When this pin is

logic low, all channels operate in automatic PWM/PSM mode, and the PSMx_ON settings in Register 6 are ignored.

VREG

Output of the Internal 5.1 V Linear Regulator. Connect a 1 µF ceramic capacitor between this pin and ground.

FB3

Feedback Sensing Input for Channel 3.

COMP3

Error Amplifier Output for Channel 3. Connect an RC network from this pin to ground.

SS34

Connect a resistor divider from this pin to VREG and ground to configure the soft start time for Channel 3 and

Channel 4 (see the Soft Start section).

EN3

Enable Input for Channel 3. An external resistor divider can be used to set the turn-on threshold.

EPAD

Exposed Pad (Analog Ground). The exposed pad must be connected and soldered to an external ground plane.

ADP5050ACPZ-R7 Datasheet(PDF) 12 Page - Analog Devices

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