ADP5050ACPZ-R7 datasheet(47/60 Pages) AD

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Data Sheet

ADP5050

Rev. 0 | Page 47 of 60

Register 8 is used to configure the switching frequency for Channel 1 and Channel 3 and to configure the phase shift for Channel 2,

Channel 3, and Channel 4 with respect to Channel 1 (0˚). The default values for the Channel 1 and Channel 3 switching frequencies

can be programmed by factory fuse.

Table 33. Register 8 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FREQ3

FREQ1

PHASE4[1:0]

PHASE3[1:0]

PHASE2[1:0]

Table 34. SW_CFG Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

FREQ3

R/W

The default value can be programmed by factory fuse.

0 = switching frequency for Channel 3 is the same as the master frequency set by the RT pin.

1 = switching frequency for Channel 3 is half the master frequency set by the RT pin.

FREQ1

R/W

The default value can be programmed by factory fuse.

0 = switching frequency for Channel 1 is the same as the master frequency set by the RT pin.

1 = switching frequency for Channel 1 is half the master frequency set by the RT pin.

[5:4]

PHASE4[1:0]

R/W

These bits configure the phase shift for Channel 4 with respect to Channel 1 (0°).

00 = 0° phase shift.

01 = 90° phase shift.

10 = 180° phase shift (default).

11 = 270° phase shift.

[3:2]

PHASE3[1:0]

R/W

These bits configure the phase shift for Channel 3 with respect to Channel 1 (0°).

00 = 0° phase shift (default).

01 = 90° phase shift.

10 = 180° phase shift.

11 = 270° phase shift.

[1:0]

PHASE2[1:0]

R/W

These bits configure the phase shift for Channel 2 with respect to Channel 1 (0°).

00 = 0° phase shift.

01 = 90° phase shift.

10 = 180° phase shift (default).

11 = 270° phase shift.

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