FDMF6840C datasheet(13/19 Pages) ONSEMI

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Adaptive Gate Drive Circuit

The driver

IC advanced design ensures

minimum

MOSFET dead-time, w hile eliminating potential shoot-

through (cross-conduction) currents. It senses the state

of the MOSFETs and adjusts the gate drive adaptively

to ensure they do not conduct simultaneously. Figure 27

provides the relevant timing w aveforms. To prevent

overlap dur ing the LOW-to-HIGH sw itching transition

(Q2 off to Q1 on), the adaptive c ircuitry monitors the

voltage at the GL pin. When the PWM signal goes

HIGH, Q2 begins to turn off after a propagation delay

(tPD_PHGLL). Once the GL pin is discharged below 1.0 V,

Q1 begins to turn on after adaptive delay tD_DEADON.

To preclude overlap during the HIGH-to-LOW transition

(Q1 off to Q2 on), the adaptive c ircuitry monitors the

voltage at the GH-to- PHASE pin pair. When the PWM

signal goes LOW, Q1 begins to turn off after a

propagation delay (tPD_PLGHL). Once the voltage across

GH-to- PHASE falls below 2.2 V, Q2 begins to turn on

after adaptive delay tD_DEADOFF.

Figure 27.

PWM and 3-StateTim ing Diagram

tPD_TSGHH

VSWH

tPD_PHGLL

tD_HOLD-OFF

90%

Exit

3-state

1.0V

PWM

VIL_PWM

VIH_PWM

VTRI_HI

VIH_PWM

10%

tR_GL

tD_HOLD-OFF

Exit

3-state

VIH_PWM

VTRI_HI

VTRI_LO

VIL_PWM

tPD_PLGHL

tPD_TSGHH

DCM

tF_GH

tR_GH

tD_HOLD-OFF

10%

CCM

DCM

Exit

3-state

90%

10%

90%

Enter

3-state

Enter

3-state

tD_DEADOFF

tD_DEADON

Enter

3-state

tF_GL

VIN

VOUT

2.2V

tPD_TSGLH

Notes:

tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal.

Example (tPD_PHGLL – PWMgoing HIGH to LS VGS (GL) going LOW)

tD_xxx = delay from ICgenerated signal to IC generatedsignal. Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH)

PWM

Exiting 3-state

tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS

tPD_TSGHH = PWM 3-state to HIGHtoHS VGS rise, VIH_PWM to 10% HS VGS

tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS

tPD_TSGLH = PWM 3-state to LOW to LS VGS rise,VIL_PWM to 10% LS VGS

tPD_PHGHH = PWM rise to HS VGS rise,VIH_PWM to10% HS VGS (SMOD#held LOW)

SMOD#

Dead Times

tPD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS

tD_DEADON = LS VGS fall to HS VGS rise,LS-comptrip value (~1.0V GL) to 10% HS VGS

tPD_SHGLH = SMOD# riseto LS VGS rise, VIH_SMOD to 10% LS VGS

tD_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value(~2.2V VSWH) to 10% LS VGS

FDMF6840C Datasheet(PDF) 13 Page - ON Semiconductor

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