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SPC560P50L3 Datasheet(PDF) 96 Page - STMicroelectronics |
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SPC560P50L3 Datasheet(HTML) 96 Page - STMicroelectronics |
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96 / 112 page ![]() Electrical characteristics SPC560P44Lx, SPC560P50Lx 96/112 Doc ID 14723 Rev 9 Figure 29. DSPI classic SPI timing – Master, CPHA = 0 11 tSUO CC D Data valid (after SCK edge) Master (MTFE = 0) — 12 ns Slave — 36 Master (MTFE = 1, CPHA = 0) — 12 Master (MTFE = 1, CPHA = 1) — 12 12 tHO CC D Data hold time for outputs Master (MTFE = 0) –2 — ns Slave 6 — Master (MTFE = 1, CPHA = 0) 6 — Master (MTFE = 1, CPHA = 1) –2 — 1. All timing is provided with 50 pF capacitance on output, 1 ns transition time on input signal. Table 42. DSPI timing(1) (continued) No. Symbol C Parameter Conditions Value Unit Min Max Data Last Data First Data First Data Data Last Data SIN SOUT PCSx SCK Output 4 9 12 1 11 10 4 SCK Output (CPOL=0) (CPOL=1) 3 2 Note: Numbers shown reference Table 42. |
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