SPC560P50L3 datasheet(77/112 Pages) STMICROELECTRONICS

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SPC560P44Lx, SPC560P50Lx

Electrical characteristics

Doc ID 14723 Rev 9

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CJITTER

CLKOUT period

jitter(6),(7),(8),(9)

Short-term jitter(10)

fSYS maximum

−44

% fCLKOUT

Long-term jitter (avg.

over 2 ms interval)

fPLLIN = 16 MHz

(resonator)

, fPLLCLK at

64 MHz, 4000 cycles

—10

tlpll

PLL lock time (11), (12)

——

200

µs

tdc

Duty cycle of reference

—40

fLCK

Frequency LOCK range

—

−66

% fSYS

fUL

Frequency un-LOCK range

—

-18

% fSYS

fCS

fDS

Modulation depth

Center spread

±0.25

±4.0(13)

% fSYS

Down spread

−0.5

−8.0

fMOD

Modulation frequency(14)

——

kHz

VDD_LV_CORx = 1.2 V ±10%; VSS = 0 V; TA = –40 to 125 °C, unless otherwise specified

Considering operation with PLL not bypassed

“Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self-clocked mode.

Self-clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR

window.

fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced

mode.

This value is determined by the crystal manufacturer and board design.

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER

percentage for a given interval.

Proper PC board layout procedures must be followed to achieve specifications.

Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either

fCS or fDS (depending on whether center spread or down spread modulation is enabled).

10. Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.

11. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this

PLL, load capacitors should not exceed these limits.

12. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the

synthesizer control register (SYNCR).

13. This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).

14. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.

Table 31.

FMPLL electrical characteristics (continued)

Symbol

Parameter

Conditions(1)

Value

Unit

Min

Max

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