SPC560P50L3 datasheet(84/112 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC560P44Lx, SPC560P50Lx

84/112

Doc ID 14723 Rev 9

tADC_PU SR —

ADC power-up delay (time

needed for ADC to settle

exiting from software power

down; PWDN bit = 0)

——

—

1.5

µs

(10)

—D

ADC input sampling

capacitance

——

—

2.5

CP1

(10)

— D ADC input pin capacitance 1

—

CP2

(10)

— D ADC input pin capacitance 2

—

RSW1

(10) —D

Internal resistance of analog

source

VDD_HV_ADC =

5V± 10%

——

0.6

VDD_HV_ADC =

3.3 V ± 10%

——

RAD

(10)

—D

Internal resistance of analog

source

——

—

IINJ

—

T Input current injection

Current injection

on one ADC input,

different from the

converted one.

Remains within

TUE spec.

–5

—

INL

CC P Integral non-linearity

No overload

–1.5

—

1.5

LSB

DNL

CC P Differential non-linearity

No overload

–1.0

—

1.0

LSB

OSE

CC T Offset error

—

±1

—

LSB

CC T Gain error

—

±1

—

LSB

TUE

CC P

Total unadjusted error without

current injection

—

–2.5

—

2.5

LSB

TUE

CC T

Total unadjusted error with

current injection

—–3

—

LSB

VDD = 3.3 V to 3.6 V / 4.5 V to 5.5 V, TA = –40 °C to TA MAX, unless otherwise specified and analog input voltage from

VSS_HV_ADCx to VDD_HV_ADCx.

VAINx may exceed VSS_HV_AD and VDD_HV_AD limits, remaining on absolute maximum ratings, but the results of the

conversion will be clamped respectively to 0x000 or 0x3FF.

Not allowed to refer this voltage to VDD_HV_ADV1, VSS_HV_ADV1

Not allowed to refer this voltage to VDD_HV_ADV0, VSS_HV_ADV0

AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.

When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which precision is lost.

During the sample time the input capacitance CS can be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the

sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample

clock tADC_S depend on programming.

This parameter includes the sample time tADC_S.

20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.

10. See Figure 16.

Table 33.

ADC conversion characteristics (continued)

Symbol

Parameter

Conditions(1)

Value

Unit

Min

Typ

Max

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