1

2

3

4

5

6

7

14

13

12

11

10

9

8

NC − No internal connection

NC

3V3

IN1

AGND

IN2

CLF

ILIM

NC

VDD

PVDD

OUT1

OUT2

PGND

CS

UCD7201

www.ti.com

SLUS645F – FEBRUARY 2005 – REVISED DECEMBER 2014

5 Description (Continued)

For fast switching speeds, the UCD7201 output stages use the TrueDrive™ output architecture, which delivers

rated current of ±4 A into the gate of a MOSFET during the Miller plateau region of the switching transition. It

also includes a 3.3-V, 10-mA linear regulator to provide power to the digital controller.

For similar applications requiring direct start-up capability from higher voltages such as the 48-V telecom input

line, the UCD7601 includes a 110-V high-voltage startup circuit.

The UCD7K driver family is compatible with standard 3.3-V I/O ports of DSPs, Microcontrollers, or ASICs.

UCD7201 is offered in a PowerPAD™ HTSSOP-14 package.

6 Pin Configuration and Functions

PWP

14 PIN

Top View

Pin Functions

PIN

I/O

FUNCTION

NO.

NAME

1

NC

-

No Connection

Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA of

2

3V3

O

current. Place 0.22

μF of ceramic capacitance from this pin to ground.

The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2

3

IN1

I

MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry from any

external noise.

4

AGND

-

Analog ground return.

The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2

5

IN2

I

MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry from any

external noise.

Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output of the

6

CLF

O

driver is forced low and the current limit flag (CLF) is set high. The CLF signal is latched high until the

device receives the next rising edge on the IN pin.

Current limit threshold set pin. The current limit threshold can be set to any value between 0.25 V

7

ILIM

I

and 1.0 V. The default value while open is 0.5 V.

Current sense pin. Fast current limit comparator connected to the CS pin is used to protect the power

8

CS

I

stage by implementing cycle-by-cycle current limiting.

9

PGND

-

Power ground return. The pin should be connected very closely to the source of the power MOSFET.

10

OUT2

O

The high-current TrueDrive™ driver output.

11

OUT1

O

The high-current TrueDrive™ driver output.

Supply pin provides power for the output drivers. It is not connected internally to the VDD supply rail.

12

PVDD

I

The bypass capacitor for this pin should be returned to PGND.

Supply input pin to power the driver. The UCD7K devices accept an input range of 4.5 V to 15 V.

13

VDD

I

Bypass the pin with at least 4.7

μF of capacitance, returned to AGND.

14

NC

-

No Connection.

Copyright © 2005–2014, Texas Instruments Incorporated

Submit Documentation Feedback

3

Product Folder Links: UCD7201