ATmega48 datasheet(41/340 Pages) ATMEL

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7530H–AVR–02/09

ATmega48/88/168 Automotive

7.7.6

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The

most important is then to ensure that no pins drive resistive loads. In sleep modes where both

the I/O clock (clk

I/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will

be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 67 for details on

which pins are enabled. If the input buffer is enabled and the input signal is left floating or have

an analog signal level close to V

CC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V

CC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and

DIDR0). Refer to “Digital Input Disable Register 1 – DIDR1” on page 236 and “Digital Input Dis-

able Register 0 – DIDR0” on page 253 for details.

7.7.7

On-chip Debug System

If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the

main clock source is enabled and hence always consumes power. In the deeper sleep modes,

this will contribute significantly to the total current consumption.

System Control and Reset

8.0.1

Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution

from the Reset Vector. For the ATmega168, the instruction placed at the Reset Vector must be a

JMP – Absolute Jump – instruction to the reset handling routine. For the ATmega48 and

ATmega88, the instruction placed at the Reset Vector must be an RJMP – Relative Jump –

instruction to the reset handling routine. If the program never enables an interrupt source, the

Interrupt Vectors are not used, and regular program code can be placed at these locations. This

is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in

the Boot section or vice versa (ATmega88/168 only). The circuit diagram in Figure 8-1 shows the

reset logic. Table 8-1 on page 43 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes

active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal

reset. This allows the power to reach a stable level before normal operation starts. The time-out

period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-

ferent selections for the delay period are presented in “Clock Sources” on page 25.

ATmega48 Datasheet(PDF) 41 Page - ATMEL Corporation

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