ATmega48 datasheet(84/340 Pages) ATMEL

84 / 340 page

7530H–AVR–02/09

ATmega48/88/168 Automotive

• Bit 1 - PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 1 is enabled. Any change on any enabled PCINT14..8 pin will cause an inter-

rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1

Interrupt Vector. PCINT14..8 pins are enabled individually by the PCMSK1 Register.

• Bit 0 - PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt.

The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter-

rupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.

11.0.5

Pin Change Interrupt Flag Register - PCIFR

• Bit 7..3 - Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 2 - PCIF2: Pin Change Interrupt Flag 2

When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set

(one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

• Bit 1 - PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set

(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

• Bit 0 - PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set

(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

Bit

6543

210

–

––––

PCIF2

PCIF1

PCIF0

PCIFR

Read/Write

RRRR

R/W

Initial Value

0000

000

ATmega48 Datasheet(PDF) 84 Page - ATMEL Corporation

ATmega48 Datasheet(HTML) 84 Page - ATMEL Corporation

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