ATmega48 datasheet(14/340 Pages) ATMEL

14 / 340 page

7530H–AVR–02/09

ATmega48/88/168 Automotive

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in this example.

4.8.1

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-

mum. After four clock cycles the program vector address for the actual interrupt handling routine

is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.

The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If

an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed

before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt

execution response time is increased by four clock cycles. This increase comes in addition to the

start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock

cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is

incremented by two, and the I-bit in SREG is set.

AVR ATmega48/88/168 Memories

This section describes the different memories in the ATmega48/88/168. The AVR architecture

has two main memory spaces, the Data Memory and the Program Memory space. In addition,

the ATmega48/88/168 features an EEPROM Memory for data storage. All three memory spaces

are linear and regular.

5.1

In-System Reprogrammable Flash Program Memory

The ATmega48/88/168 contains 4/8/16K bytes On-chip In-System Reprogrammable Flash

memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is orga-

nized as 2/4/8K x 16. For software security, the Flash Program memory space is divided into two

sections, Boot Loader Section and Application Program Section in ATmega88 and ATmega168.

ATmega48 does not have separate Boot Loader and Application Program sections, and the

SPM instruction can be executed from the entire Flash. See SELFPRGEN description in section

“Store Program Memory Control and Status Register – SPMCSR” on page 258 and page 268for

more details.

The F lash memory has an endurance of at least 75,000 write/erase cycles. The

ATmega48/88/168 Program Counter (PC) is 11/12/13 bits wide, thus addressing the 2/4/8K pro-

gram memory locations. The operation of Boot Program section and associated Boot Lock bits

for software protection are described in detail in “Self-Programming the Flash, ATmega48” on

page 256 and “Boot Loader Support – Read-While-Write Self-Programming, ATmega88 and

ATmega168” on page 263. “Memory Programming” on page 278 contains a detailed description

on Flash Programming in SPI- or Parallel Programming mode.

Assembly Code Example

sei

; set Global Interrupt Enable

sleep

; enter sleep, waiting for interrupt

; note: will enter sleep before any pending interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

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