ATmega48 datasheet(165/340 Pages) ATMEL

165 / 340 page

165

7530H–AVR–02/09

ATmega48/88/168 Automotive

17. USART0

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a

highly flexible serial communication device. The main features are:

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High Resolution Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data OverRun Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

• Multi-processor Communication Mode

• Double Speed Asynchronous Communication Mode

The USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 192. The

Power Reduction USART bit, PRUSART0, in “Power Reduction Register - PRR” on page 39

must be disabled by writing a logical zero to it.

17.1

Overview

A simplified block diagram of the USART Transmitter is shown in Figure 17-1. CPU accessible

I/O Registers and I/O pins are shown in bold.

ATmega48 Datasheet(PDF) 165 Page - ATMEL Corporation