WM8785

Production Data

w

PD Rev 4.1 December 2006

28

REGISTER MAP

REGISTER ADDRESS REMARK BIT8

BIT7

BIT6 BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

DEFAULT

R0(00h)

00_0000

Sample

Rate

And

Audio IF

Format

0

0

FORMAT

OSR

MCR

0_0000_0011

R1(01h)

00_0001

Audio IF

Format

And

TDM

0

DEVNO

LRSWP

BCLKINV

LRP

WL

0_0000_1010

R2(02h)

00_0010

Signal

Control

TDM

0

PWRDNL

PWRDNR

SDODIS

HPFL

HPFR

0_0000_0011

R7(07h)

00_0111

Reset

Writing to reg 7 will cause software reset

0_0000_0000

Table 14 Register Map for Control Interface

Notes:

1.

All unused register bits should be set to zero

2.

The interface will initiate SWRB whenever R7 is addressed, regardless of the data input.

3.

SWRB is released on the next register write or after 4 MCLK cycles (which ever occurs first).

4.

Until the SWRB is released, DOUT is forced to zero.

5.

DOUT remains zero for a count of 32 sample clocks SWRB is released, this count is driven by MCLK and is

independent of any external LRCLK.