Production Data

WM8785

w

PD Rev 4.1 December 2006

21

DATA OUT PIN DISABLE

To prevent any communication problems on the Audio Interface, the interface can be disabled

(DOUT tristated and floating) using the SDODIS bit.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2(02h)

HP Filter ,

Output

disable,

Power down,

Mono mode

2

SDODIS

0

DOUT serial data pin disable

0 = DOUT pin enabled

1 = DOUT pin off (high impedance)

Table 3 Oversampling Ratio Selection

CONTROL INTERFACE

SELECTION OF CONTROL MODE

The WM8785 is controlled by writing to registers through a serial control interface. A control word

consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is

accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each

control register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The

CSB pin is sampled at power-up and selects the interface format. After power-up the pin is available

to latch in control data in 3-wire interface mode.

Figure 25 Control Interface Mode Selection

CSB PIN STATUS

INTERFACE FORMAT

Low

2 wire

High

3 wire

Table 4 Control Interface Mode Selection

SETUP/HOLD

TIME

tpusetup

250us

tpuhold

250us

Table 5 Control Interface Mode Selection