Production Data

WM8785

w

PD Rev 4.1 December 2006

19

Figure 23 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave)

Figure 24 DSP/PCM Mode Audio Interface (mode B, LRP=1, Slave)

AUDIO INTERFACE CONTROL

The register bits controlling the audio interface are summarised below. Note that dynamically

changing the software format may cause erroneous operation of the interfaces and is therefore not

recommended.

All ADC data is 2’s complement. The length of the digital audio data is programmable at 16/20/24 or

32 bits, as shown below. The ADC digital filters process data using 24 bits. If the WM8785 is

programmed to output 16 or 20 bit data then it strips the LSBs from the 24 bit data. If the device is

programmed to output 32 bits then it packs the LSBs with zeros.

In master mode LRCLK and BCLK are generated on chip. In slave mode they are received from an

external source.