WM8785

Production Data

w

PD Rev 4.1 December 2006

20

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R0 (00h)

Sample Rate

and Digital Audio

Interface Format

6:5

FORMAT

10

Audio Data Format Select

11: DSP Format

10: I

01: Left justified

00: Right justified

1:0

WL

10

Audio Data Word Length

11: 32 bits (see Note)

10: 24 bits

01: 20 bits

00: 16 bits

right, left and I

LRCLK polarity

1 = invert LRCLK polarity

0 = normal LRCLK polarity

2

LRP

0

DSP Mode – A/B select

1 = MSB is available on 1st

BCLK rising edge after LRC

rising edge (mode B)

0 = MSB is available on 2nd

BCLK rising edge after LRC

rising edge (mode A)

3

BCLKINV

0

BCLK invert bit (for master and

slave modes)

0 = BCLK not inverted

1 = BCLK inverted

R1 (01h)

Digital Audio

Interface Format

and TDM

4

LRSWAP

0

Left/Right channel swap

1 = swap left and right DAC

data in audio interface

0 = output left and right data as

normal

Table 1 Audio Data Format Control

Note: Right Justified mode does not support 32-bit data. If WL=11 in Right justified mode, the actual

word length is 24 bits.

DIGITAL HIGH PASS

The high pass filter can be enabled using the HPFL and HPFR bits (see digital filter characteristics)

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0

HPFR

1

Digital High Pass Filter, Right Channel

0 = HPF Off

1 = HPF On

R2(02h)

HPfilter ,

Output

disable,

Power down,

Mono mode

1

HPFL

1

Digital High Pass Filter, Left Channel

0 = HPF Off

1 = HPF On

Table 2 Oversampling Ratio Selection

The high pass filter should only be disabled for procedures such as DC offset calibration. It should be

noted that the output range of the ADC with a DC level applied and HPF disabled is as follows:

Maximum code: 7FDFB0

Minimum code: 802033