STMIPID02SLASHTR datasheet(11/50 Pages) STMICROELECTRONICS

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Ball name

Type

Description

XSDN

Input

Chip shutdown

Control interface

SCL

Input

Host I2C clock

SDA

BiDir

Host I2C data

Dual lane input data interface

CLKP1, CLKN1

Input

MIPI CSI-2 receiver 1 DDR clock input,

MIPI D-PHY physical layer, doubles as

CCP2 strobe/clock input in SMIA CCP2

Class 2 mode

DATA1P1, DATA1N1

Input

MIPI CSI-2 receiver 1 data lane 1, MIPI

D-PHY physical layer, doubles as CCP2

data input in SMIA CCP2 Class 2 mode

DATA2P1, DATA2N1

Input

MIPI CSI-2 receiver 1 data lane 2, MIPI

D-PHY physical layer

Single lane input data interface

CLKP2, CLKN2

Input

MIPI CSI-2 receiver 2 DDR clock input,

MIPI D-PHY physical layer, doubles as

CCP2 strobe/clock input in SMIA CCP2

Class 2 mode

DATA1P2, DATA1N2

Input

MIPI CSI-2 receiver 2 data lane, MIPI D-

PHY physical layer, doubles as CCP2

data input in SMIA CCP2 Class 2 mode

Output data interface

D[11:0]

Output

Parallel video 12-bit data output

PCLK

Output

Pixel clock: PCLK rising edge is used to

sample D[11:0], HSYNC and VSYNC.

PCLK polarity is programmable

HSYNC

Output

Horizontal synchronization: HSYNC is

high during active video and low during

the horizontal blanking periods. HSYNC

polarity is programmable

VSYNC

Output

Vertical synchronization: VSYNC is high

during active video and low during the

vertical blanking periods. VSYNC

polarity is programmable

Power on reset (POR)

POR_SGN

BiDir

Power on reset signal

POR_TST

Input

Power on reset test signal, should be set

to ground for internal POR

Voltage regulator

VDDOUT_LDO

Power

LDO 1.2 V output

Test interface (ST internal use)

LDO_TST

Input

LDO regulator test mode

TDI

Input

Test data input

TMS

Input

Test mode

TCK

Input

Test clock

TDO

Output

Test data out

STMIPID02

Ball assignment and description

DS12803 - Rev 1

page 11/50

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