STMIPID02SLASHTR datasheet(44/50 Pages) STMICROELECTRONICS

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PCB layout guide

The usual good PCB design rules should be observed for the layout of the STMIPID02.

Power and ground planes should be used to supply power to the STMIPID02.

The high-speed signal pairs (CLKP1, CLKN1), (DATA1P1, DATA1N1), (DATA2P1, DATA2N1), (CLKP2, CLKN2)

and (DATA1P2, DATA1N2) should be routed as balanced transmission lines with a characteristic differential

impedance (Zodiff) of 100 Ω, and matched in length.

The delay difference between Cclock lane, data lane1 and data lane2 should be less than 5 ps.

The total series resistance of the CSI line should be less than 5 Ω.

For more details, please refer to the MIPI Alliance Specification for D-PHY”, version 0.90.00, 8 October 2007,

Section 7 "Interconnect and Lane Configuration" and Annex B "Interconnect Design Guidelines".

The output interface clock (PCLK) should be 50 Ω adapted.

The output clock (PCLK) and data line length from the STMIPID02 to the host should be as small as possible to

avoid reflection effects.

All passive components for the STMIPID02 should be placed in close proximity to the device, including the

decoupling capacitors.

The recommended pull up value of the I2C is in the range 2480 Ω to2780 Ω for a bus load capacitance below 100

pF.

The recommended capacitor values are:

•

10 nF on VDD1V2

•

100 nF on VDDIN_LDO and VDDE_1V8

•

1 µF (low ESR <1 Ω) on VDDOUT_LDO

STMIPID02

PCB layout guide

DS12803 - Rev 1

page 44/50

STMIPID02/TR Datasheet(PDF) 44 Page - STMicroelectronics