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STM32G47PBY6TR Datasheet(PDF) 187 Page - STMicroelectronics

No. de pieza STM32G47PBY6TR
Descripción Electrónicos  Arm® Cortex®-M4 32-bit MCUFPU, up to 512 KB Flash, 170 MHz / 213DMIPS, 128 KB SRAM, rich analog, math accelerator
PDF  229 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32G47PBY6TR Datasheet(HTML) 187 Page - STMicroelectronics

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DS12712 Rev 3
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STM32G473xB STM32G473xC STM32G473xE
Electrical characteristics
194
Figure 46. Synchronous non-multiplexed NOR/PSRAM read timings
Table 99. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2)(3)
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
R*THCLK - 0.5
-
ns
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
-
1.5
td(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x= 0…2)
R*THCLK/2 + 1
-
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
-
2.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
3.5
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
-
4
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25)
R*THCLK/2+- 1
-
td(CLKL-NOEL)
FMC_CLK low to FMC_NOE low
-
2
td(CLKH-NOEH)
FMC_CLK high to FMC_NOE high
R*THCLK/2 + 1
-
tsu(DV-CLKH)
FMC_D[15:0] valid data before FMC_CLK high
2
-
th(CLKH-DV)
FMC_D[15:0] valid data after FMC_CLK high
4
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
1.5
-
ns
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
4
-
FMC_CLK
FMC_NEx
FMC_A[25:0]
FMC_NOE
FMC_D[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK)
tw(CLK)
Data latency = 0
td(CLKL-NExL)
td(CLKH-NExH)
td(CLKL-AV)
td(CLKH-AIV)
td(CLKL-NOEL)
td(CLKH-NOEH)
tsu(DV-CLKH)
th(CLKH-DV)
tsu(DV-CLKH)
th(CLKH-DV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
tsu(NWAITV-CLKH)
t h(CLKH-NWAITV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
MS32759V1
FMC_NADV
td(CLKL-NADVL)
td(CLKL-NADVH)



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