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STM32G47PBY6TR Datasheet(PDF) 19 Page - STMicroelectronics

No. de pieza STM32G47PBY6TR
Descripción Electrónicos  Arm® Cortex®-M4 32-bit MCUFPU, up to 512 KB Flash, 170 MHz / 213DMIPS, 128 KB SRAM, rich analog, math accelerator
PDF  229 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
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STM32G47PBY6TR Datasheet(HTML) 19 Page - STMicroelectronics

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DS12712 Rev 3
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STM32G473xB STM32G473xC STM32G473xE
Functional overview
46
3.5
Embedded SRAM
STM32G473xB/xC/xE devices feature 128 Kbytes of embedded SRAM. This SRAM is split
into three blocks:
80 Kbytes mapped at address 0x2000 0000 (SRAM1). The CM4 can access the
SRAM1 through the System Bus. The first 32 Kbyte of SRAM1 support hardware parity
check.
16 Kbytes mapped at address 0x2001 4000 (SRAM2). The CM4 can access the
SRAM2 through the System bus. SRAM2 can be retained in standby modes.
32 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is accessed by the CPU
through I-Code/D-Code bus for maximum performance.
It is also aliased at 0x2001 8000 address to be accessed by all masters (CPU, DMA1,
DMA2) through SBUS contiguously to SRAM1 and SRAM2. The CCM SRAM supports
hardware parity check and can be write-protected with 1 Kbyte granularity.
The memory can be accessed in read/write at max CPU clock speed with 0 wait states.
3.6
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM, FSMC, QUADSPI, AHB and APB peripherals). It also ensures a
seamless and efficient operation even when several high-speed peripherals work
simultaneously.
Figure 2. Multi-AHB bus matrix
MS52814V1
Cortex
®-M4
with FPU
DMA1
DMA2
AHB2
peripherals
AHB1
peripherals
CCM
SRAM
SRAM1
FLASH
512 KB
ICode
DCode
BusMatrix-S
SRAM2
QUADSPI



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