LTC2412IGN datasheet(26/36 Pages) LINER

26 / 36 page

LTC2412

2412f

APPLICATIO S I FOR ATIO

various values of source resistance imbalance between

the IN+ and IN– pins when large CIN values are used.

If possible, it is desirable to operate with the input signal

common mode voltage very close to the reference signal

common mode voltage as is the case in the ratiometric

measurement of a symmetric bridge. This configuration

eliminates the offset error caused by mismatched source

impedances.

The magnitude of the dynamic input current depends upon

the size of the very stable internal sampling capacitors and

upon the accuracy of the converter sampling clock. The

accuracy of the internal clock over the entire temperature

and power supply range is typical better than 0.5%. Such

a specification can also be easily achieved by an external

clock. When relatively stable resistors (50ppm/

°C) are

used for the external source impedance seen by IN+ and

IN–, the expected drift of the dynamic current, offset and

gain errors will be insignificant (about 1% of their respec-

tive values over the entire temperature and voltage range).

Even for the most stringent applications, a one-time

calibration operation may be sufficient.

In addition to the input sampling charge, the input ESD

protection diodes have a temperature dependent leakage

current. This current, nominally 1nA (

±10nA max), results

in a small offset shift. A 100

Ω source resistance will create

a 0.1

µV typical and 1µV maximum offset voltage.

Reference Current

In a similar fashion, the LTC2412 samples the differential

reference pins REF+ and REF– transfering small amount of

charge to and from the external driving circuits thus

producing a dynamic reference current. This current does

not change the converter offset, but it may degrade the

gain and INL performance. The effect of this current can be

analyzed in the same two distinct situations.

For relatively small values of the external reference capaci-

tors (CREF < 0.01µF), the voltage on the sampling capacitor

settles almost completely and relatively large values for

the source impedance result in only small errors. Such

values for CREF will deteriorate the converter offset and

gain performance without significant benefits of reference

filtering and the user is advised to avoid them.

Larger values of reference capacitors (CREF > 0.01µF) may

be required as reference filters in certain configurations.

Such capacitors will average the reference sampling charge

and the external source resistance will see a quasi con-

stant reference differential impedance. When FO = LOW

(internal oscillator and 60Hz notch), the typical differential

reference resistance is 1.3M

Ω which will generate a gain

error of approximately 0.38ppm at full-scale for each ohm

of source resistance driving REF+ or REF–. When FO =

HIGH (internal oscillator and 50Hz notch), the typical

differential reference resistance is 1.56M

Ω which will

generate a gain error of approximately 0.32ppm at full-

scale for each ohm of source resistance driving REF+ or

REF–. When FO is driven by an external oscillator with a

frequency fEOSC (external conversion clock operation), the

typical differential reference resistance is 0.20 • 1012/

fEOSCΩ and each ohm of source resistance drving REF+ or

REF– will result in 2.47 • 10–6 • fEOSCppm gain error at full-

scale. The effect of the source resistance on the two

reference pins is additive with respect to this gain error.

The typical +FS and –FS errors for various combinations

of source resistance seen by the REF+ and REF– pins and

external capacitance CREF connected to these pins are

shown in Figures 18, 19, 20 and 21.

Figure 17. Offset Error vs Common Mode Voltage

(VINCM = IN+ = IN–) and Input Source Resistance

Imbalance (

∆RIN = RSOURCEIN+ – RSOURCEIN–) for

Large CIN Values (CIN ≥ 1µF)

VINCM (V)

0.5

1.5

2.5

3.5

4.5

2412 F17

120

100

–20

–40

–60

–80

–100

–120

FO = GND

TA = 25°C

RSOURCEIN– = 500Ω

CIN = 10µF

VCC = 5V

REF+ = 5V

REF – = GND

IN+ = IN– = VINCM

∆RIN = +400Ω

∆RIN = +200Ω

∆RIN = +100Ω

∆RIN = 0Ω

∆RIN = –100Ω

∆RIN = –200Ω

∆RIN = –400Ω

LTC2412IGN Datasheet(PDF) 26 Page - Linear Technology

LTC2412IGN Datasheet(HTML) 26 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Descarga

Enlace URL