LTC2412IGN datasheet(20/36 Pages) LINER

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LTC2412

2412f

APPLICATIO S I FOR ATIO

device returns to the sleep state and the conversion result

is held in the internal static shift register.

If CS remains LOW longer than tEOCtest, the first rising

edge of SCK will occur and the conversion result is serially

shifted out of the SDO pin. The data output cycle concludes

after the 32nd rising edge. Data is shifted out the SDO pin

on each falling edge of SCK. The internally generated serial

clock is output to the SCK pin. This signal may be used to

shift the conversion result into external circuitry. EOC can

be latched on the first rising edge of SCK and the last bit

of the conversion result on the 32nd rising edge of SCK.

After the 32nd rising edge, SDO goes HIGH (EOC = 1), SCK

stays HIGH and a new conversion starts.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first and 32nd rising edge

of SCK, see Figure 9. On the rising edge of CS, the device

aborts the data output state and immediately initiates a

new conversion. This is useful for systems not requiring

all 32 bits of output data, aborting an invalid conversion

cycle, or synchronizing the start of a conversion. If CS is

pulled HIGH while the converter is driving SCK LOW, the

internal pull-up is not available to restore SCK to a logic

HIGH state. This will cause the device to exit the internal

serial clock mode on the next falling edge of CS. This can

be avoided by adding an external 10k pull-up resistor to

the SCK pin or by never pulling CS HIGH when SCK is LOW.

Whenever SCK is LOW, the LTC2412’s internal pull-up at

pin SCK is disabled. Normally, SCK is not externally driven

if the device is in the internal SCK timing mode. However,

certain applications may require an external driver on SCK.

If this driver goes Hi-Z after outputting a LOW signal, the

LTC2412’s internal pull-up remains disabled. Hence, SCK

remains LOW. On the next falling edge of CS, the device is

switched to the external SCK timing mode. By adding an

external 10k pull-up resistor to SCK, this pin goes HIGH

once the external driver goes Hi-Z. On the next CS falling

edge, the device will remain in the internal SCK timing

mode.

A similar situation may occur during the sleep state when

CS is pulsed HIGH-LOW-HIGH in order to test the

conversion status. If the device is in the sleep state (EOC

= 0), SCK will go LOW. Once CS goes HIGH (within the time

period defined above as tEOCtest), the internal pull-up is

activated. For a heavy capacitive load on the SCK pin, the

Figure 8. Internal Serial Clock, Single Cycle Operation

SDO

SCK

(INTERNAL)

MSB

SIG

CH0/CH1

BIT 0

LSB24

BIT 5

TEST EOC

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

EOC

BIT 31

SLEEP

DATA OUTPUT

CONVERSION

2412 F08

<tEOCtest

VCC

10k

Hi-Z

TEST EOC

(OPTIONAL)

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

VCC

REF+

SCK

CH1+

CH1–

SDO

GND

114

8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

CH0+

CH0–

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

µF

2.7V TO 5.5V

LTC2412

3-WIRE

SPI INTERFACE

REF–

SLEEP

LTC2412IGN Datasheet(PDF) 20 Page - Linear Technology

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