LTC2412IGN datasheet(14/36 Pages) LINER

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LTC2412

2412f

Bit 31 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bit 30 (second output bit) is the selected channel indicator.

The bit is LOW for channel 0 and HIGH for channel 1

selected.

Bit 29 (third output bit) is the conversion result sign indi-

cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this

bit is LOW.

Bit 28 (fourth output bit) is the most significant bit (MSB)

of the result. This bit in conjunction with Bit 29 also

provides the underrange or overrange indication. If both

Bit 29 and Bit 28 are HIGH, the differential input voltage is

above +FS. If both Bit 29 and Bit 28 are LOW, the

differential input voltage is below –FS.

The function of these bits is summarized in Table 1.

Table 1. LTC2412 Status Bits

Bit 31

Bit 30

Bit 29 Bit 28

Input Range

EOC

CH0/CH1

SIG

MSB

VIN ≥ 0.5 • VREF

0 or 1

≤ VIN < 0.5 • VREF

0 or 1

–0.5 • VREF ≤ VIN < 0V

0 or 1

VIN < – 0.5 • VREF

0 or 1

Bits 28-5 are the 24-bit conversion result MSB first.

Bit 5 is the least significant bit (LSB).

Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may

be included in averaging or discarded without loss of

resolution.

Data is shifted out of the SDO pin under control of the serial

clock (SCK), see Figure 3. Whenever CS is HIGH, SDO

remains high impedance and any externally generated

SCK clock pulses are ignored by the internal data out shift

In order to shift the conversion result out of the device, CS

must first be driven LOW. EOC is seen at the SDO pin of the

device once CS is pulled LOW. EOC changes real time from

HIGH to LOW at the completion of a conversion. This

signal may be used as an interrupt for an external micro-

controller. Bit 31 (EOC) can be captured on the first rising

edge of SCK. Bit 30 is shifted out of the device on the first

falling edge of SCK. The final data bit (Bit 0) is shifted out

on the falling edge of the 31st SCK and may be latched on

the rising edge of the 32nd SCK pulse. On the falling edge

of the 32nd SCK pulse, SDO goes HIGH indicating the

initiation of a new conversion cycle. This bit serves as EOC

(Bit 31) for the next conversion cycle. Table 2 summarizes

the output data format.

As long as the voltage on the analog input pins is main-

tained within the – 0.3V to (VCC + 0.3V) absolute maximum

operating range, a conversion result is generated for any

differential input voltage VIN from –FS = –0.5 • VREF to

+FS = 0.5 • VREF. For differential input voltages greater than

+FS, the conversion result is clamped to the value corre-

sponding to the +FS + 1LSB. For differential input voltages

below –FS, the conversion result is clamped to the value

corresponding to –FS – 1LSB.

APPLICATIO S I FOR ATIO

Figure 3. Output Data Timing

MSB

SIG

CH0/CH1

262732

BIT 0

BIT 27

BIT 5

LSB24

BIT 28

BIT 29

BIT 30

SDO

SCK

EOC

BIT 31

SLEEP

DATA OUTPUT

CONVERSION

2412 F03

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