LTC2412IGN datasheet(24/36 Pages) LINER

24 / 36 page

LTC2412

2412f

APPLICATIO S I FOR ATIO

For a simple approximation, the source impedance RS

driving an analog input pin (IN+, IN–, REF+ or REF–) can be

considered to form, together with RSW and CEQ (see

Figure 11), a first order passive network with a time

constant

τ = (RS + RSW) • CEQ. The converter is able to

sample the input signal with better than 1ppm accuracy if

the sampling period is at least 14 times greater than the

input circuit time constant

τ. The sampling process on the

four input analog pins is quasi-independent so each time

constant should be considered by itself and, under worst-

case circumstances, the errors may add.

When using the internal oscillator (FO = LOW or HIGH), the

LTC2412’s front-end switched-capacitor network is clocked

at 76800Hz corresponding to a 13

µs sampling period.

Thus, for settling errors of less than 1ppm, the driving

source impedance should be chosen such that

τ≤13µs/14

= 920ns. When an external oscillator of frequency fEOSC is

used, the sampling period is 2/fEOSC and, for a settling

error of less than 1ppm,

τ ≤ 0.14/fEOSC.

Input Current

If complete settling occurs on the input, conversion re-

sults will be unaffected by the dynamic input current. An

incomplete settling of the input signal sampling process

may result in gain and offset errors, but it will not degrade

the INL performance of the converter. Figure 11 shows the

mathematical expressions for the average bias currents

flowing through the IN+ and IN– pins as a result of the

sampling charge transfers when integrated over a sub-

stantial time period (longer than 64 internal clock cycles).

The effect of this input dynamic current can be analyzed

using the test circuit of Figure 12. The CPAR capacitor

includes the LTC2412 pin capacitance (5pF typical) plus

the capacitance of the test fixture used to obtain the results

shown in Figures 13 and 14. A careful implementation can

bring the total input capacitance (CIN + CPAR) closer to 5pF

thus achieving better performance than the one predicted

by Figures 13 and 14. For simplicity, two distinct situa-

tions can be considered.

For relatively small values of input capacitance (CIN <

0.01

µF), the voltage on the sampling capacitor settles

almost completely and relatively large values for the

source impedance result in only small errors. Such values

CIN

2412 F12

VINCM + 0.5VIN

RSOURCE

IN+

LTC2412

CPAR

≅20pF

CIN

VINCM – 0.5VIN

RSOURCE

IN –

CPAR

≅20pF

Figure 12. An RC Network at IN+ and IN–

Figure 14. –FS Error vs RSOURCE at IN+ or IN– (Small CIN)

Figure 13. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)

RSOURCE (Ω)

100

10k

100k

2412 F13

VCC = 5V

REF+ = 5V

REF – = GND

IN+ = 5V

IN– = 2.5V

FO = GND

TA = 25°C

CIN = 0.01µF

CIN = 0.001µF

CIN = 100pF

CIN = 0pF

RSOURCE (Ω)

100

10k

100k

2412 F14

–10

–20

–30

–40

–50

VCC = 5V

REF+ = 5V

REF – = GND

IN+ = GND

IN– = 2.5V

FO = GND

TA = 25°C

CIN = 0.01µF

CIN = 0.001µF

CIN = 100pF

CIN = 0pF

for CIN will deteriorate the converter offset and gain

performance without significant benefits of signal filtering

and the user is advised to avoid them. Nevertheless, when

small values of CIN are unavoidably present as parasitics

LTC2412IGN Datasheet(PDF) 24 Page - Linear Technology

LTC2412IGN Datasheet(HTML) 24 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Descarga

Enlace URL