LTC2412IGN datasheet(21/36 Pages) LINER

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LTC2412

2412f

APPLICATIO S I FOR ATIO

internal pull-up may not be adequate to return SCK to a

HIGH level before CS goes low again. This is not a concern

under normal conditions where CS remains LOW after

detecting EOC = 0. This situation is easily overcome by

adding an external 10k pull-up resistor to the SCK pin.

Internal Serial Clock, 2-Wire I/O,

Continuous Conversion

This timing mode uses a 2-wire, all output (SCK and SDO)

interface. The conversion result is shifted out of the device

by an internally generated serial clock (SCK) signal, see

Figure 10. CS may be permanently tied to ground, simpli-

fying the user interface or isolation barrier.

The internal serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately 1ms after VCC exceeds 2V. An internal weak

pull-up is active during the POR cycle; therefore, the

internal serial clock timing mode is automatically selected

if SCK is not externally driven LOW (if SCK is loaded such

that the internal pull-up cannot pull the pin HIGH, the

external SCK mode will be selected).

During the conversion, the SCK and the serial data output

pin (SDO) are HIGH (EOC = 1). Once the conversion is

complete, SCK and SDO go LOW (EOC = 0) indicating the

conversion has finished and the device has entered the

data output state. The data output cycle begins on the

first rising edge of SCK and ends after the 32nd rising

edge. Data is shifted out the SDO pin on each falling edge

of SCK. The internally generated serial clock is output

to the SCK pin. This signal may be used to shift the

conversion result into external circuitry. EOC can be

latched on the first rising edge of SCK and the last bit of

the conversion result can be latched on the 32nd rising

edge of SCK. After the 32nd rising edge, SDO goes HIGH

(EOC = 1) indicating a new conversion is in progress. SCK

remains HIGH during the conversion.

Figure 9. Internal Serial Clock, Reduced Data Output Length

SDO

SCK

(INTERNAL)

>tEOCtest

MSB

SIG

CH0/CH1

BIT 8

TEST EOC

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

EOC

BIT 31

EOC

BIT 0

DATA OUTPUT

Hi-Z

DATA

OUTPUT

CONVERSION

SLEEP

2412 F09

<tEOCtest

VCC

10k

TEST EOC

(OPTIONAL)

TEST EOC

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

VCC

REF+

SCK

CH1+

CH1–

SDO

GND

114

8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

CH0+

CH0–

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

µF

2.7V TO 5.5V

LTC2412

3-WIRE

SPI INTERFACE

REF–

SLEEP

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